Patents by Inventor Hiroki Inoue

Hiroki Inoue has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20150310906
    Abstract: A highly reliable semiconductor device. In a configuration where a precharged source line is discharged to a bit line by establishing electrical continuity between the source line and the bit line through a transistor to read a potential retained at a gate of the transistor, the potential of the bit line is switched in accordance with a change in potential of the source line due to the discharge. With this configuration, the voltage between the source and drain of the transistor can be kept lower than a predetermined voltage by discharge. Accordingly, the source-drain voltage of the transistor can be kept lower than its breakdown voltage, so that the semiconductor device can have high reliability.
    Type: Application
    Filed: April 17, 2015
    Publication date: October 29, 2015
    Inventors: Takanori MATSUZAKI, Hiroki INOUE
  • Publication number: 20150311323
    Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.
    Type: Application
    Filed: June 16, 2015
    Publication date: October 29, 2015
    Inventors: Hiroki Inoue, Kiyoshi Kato, Takanori Matsuzaki, Shuhei Nagatsuka
  • Patent number: 9171630
    Abstract: To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The electrical charge of a bit line is discharged, the potential of the bit line is charged via a transistor for writing data, and the potential of the bit line which is changed by the charging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: October 27, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shuhei Nagatsuka, Hiroki Inoue, Takahiko Ishizu, Takanori Matsuzaki, Yutaka Shionoiri, Kiyoshi Kato
  • Publication number: 20150294693
    Abstract: Provided is a semiconductor device which can achieve a reduction in its area, reduction in power consumption, and operation at a high speed. A semiconductor device 10 has a structure in which a circuit 31 including a memory circuit and a circuit 32 including an amplifier circuit are stacked. With this structure, the memory circuit and the amplifier circuit can be mounted on the semiconductor device 10 while the increase in the area of the semiconductor device 10 is suppressed. Thus, the area of the semiconductor device 10 can be reduced. Further, the circuits are formed using OS transistors, so that the memory circuit and the amplifier circuit which have low off-state current and which can operate at a high speed can be formed. Therefore, a reduction in power consumption and improvement in operation speed of the semiconductor device 10 can be achieved.
    Type: Application
    Filed: April 8, 2015
    Publication date: October 15, 2015
    Inventors: Tatsuya ONUKI, Kiyoshi KATO, Yutaka SHIONOIRI, Tomoaki ATSUMI, Takanori MATSUZAKI, Hiroki INOUE, Shuhei NAGATSUKA, Yuto YAKUBO
  • Patent number: 9153589
    Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: October 6, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato, Shuhei Nagatsuka, Takanori Matsuzaki, Hiroki Inoue
  • Patent number: 9133098
    Abstract: A method for producing an organolithium compound includes the step of reacting an aromatic compound or a halogenated unsaturated aliphatic compound and a lithiating agent in the presence of a coordinating compound containing three or more elements having a coordinating ability in a molecule, at least one thereof being a nitrogen element, or a coordinating compound containing three or more oxygen elements having a coordinating ability in a molecule, at least one of the groups containing the oxygen elements having a coordinating ability being a tertiary alkoxy group, at a temperature of ?40° C. to 40° C.
    Type: Grant
    Filed: October 3, 2014
    Date of Patent: September 15, 2015
    Assignee: Nippon Soda Co., Ltd.
    Inventor: Hiroki Inoue
  • Publication number: 20150225257
    Abstract: A ballast water treatment apparatus includes a filtering device including a filter for filtering seawater, an ultraviolet irradiation device that irradiates the seawater filtered by the filter with ultraviolet light, a first path for supplying the seawater filtered by the filtering device to the ultraviolet irradiation device, a discharge water path for discharging the seawater remaining in the filtering device, a first valve provided in the first path, a second path for supplying the seawater flowing from the ultraviolet irradiation device to a ballast tank, and a control device that closes the first valve and cleans the filter by using the seawater introduced into the filtering device before the seawater filtered by the filtering device is supplied to the ultraviolet irradiation device.
    Type: Application
    Filed: May 14, 2014
    Publication date: August 13, 2015
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroki Inoue, Ryoji Harada, Kenichiro Miyatake
  • Publication number: 20150210564
    Abstract: A ballast water treatment apparatus includes a discharge path for discharging ballast water from a ballast tank that stores the ballast water, an ultraviolet irradiation device that includes an ultraviolet lamp and that irradiates the ballast water passing through the discharge path with ultraviolet light, a circulation path formed so that the ballast water circulates therethrough and is irradiated with ultraviolet light emitted from the ultraviolet lamp, a switching portion for switching a path through which the ballast water flows between the circulation path and the discharge path, and a control device that controls the switching portion so that the ballast water flows through the circulation path during a switching-on process of the ultraviolet lamp and controls the switching portion so that the ballast water flows through the discharge path when the switching on of the ultraviolet lamp is completed.
    Type: Application
    Filed: May 14, 2014
    Publication date: July 30, 2015
    Applicant: SUMITOMO ELECTRIC INDUSTRIES, LTD.
    Inventors: Hiroki Inoue, Ryoji Harada, Kenichiro Miyatake
  • Patent number: 9092042
    Abstract: One object of the present invention is to provide a regulator circuit with an improved noise margin. In a regulator circuit including a bias circuit generating a reference voltage on the basis of the potential difference between a first power supply terminal and a second power supply terminal, and a voltage regulator outputting a potential to an output terminal on the basis of a reference potential input from the bias circuit, a bypass capacitor is provided between a power supply terminal and a node to which a gate of a transistor included in the bias circuit is connected.
    Type: Grant
    Filed: June 3, 2013
    Date of Patent: July 28, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Kiyoshi Kato, Shuhei Nagatsuka, Koichiro Kamata, Tsutomu Murakawa, Takahiro Tsuji, Kaori Ikada
  • Patent number: 9076679
    Abstract: The semiconductor device includes a source line, a bit line, a signal line, a word line, memory cells connected in parallel between the source line and the bit line, a first driver circuit electrically connected to the source line and the bit line through switching elements, a second driver circuit electrically connected to the source line through a switching element, a third driver circuit electrically connected to the signal line, and a fourth driver circuit electrically connected to the word line. The memory cell includes a first transistor including a first gate electrode, a first source electrode, and a first drain electrode, a second transistor including a second gate electrode, a second source electrode, and a second drain electrode, and a capacitor. The second transistor includes an oxide semiconductor material.
    Type: Grant
    Filed: May 23, 2013
    Date of Patent: July 7, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Jun Koyama, Kiyoshi Kato, Shuhei Nagatsuka, Takanori Matsuzaki, Hiroki Inoue
  • Publication number: 20150155289
    Abstract: A semiconductor device including a nonvolatile memory cell in which a writing transistor which includes an oxide semiconductor, a reading transistor which includes a semiconductor material different from that of the writing transistor, and a capacitor are included is provided. Data is written to the memory cell by turning on the writing transistor and applying a potential to a node where a source electrode (or a drain electrode) of the writing transistor, one electrode of the capacitor, and a gate electrode of the reading transistor are electrically connected, and then turning off the writing transistor, so that the predetermined amount of charge is held in the node. Further, when a p-channel transistor is used as the reading transistor, a reading potential is a positive potential.
    Type: Application
    Filed: November 25, 2014
    Publication date: June 4, 2015
    Inventors: Hiroki Inoue, Kiyoshi Kato, Takanori Matsuzaki, Shuhei Nagatsuka
  • Publication number: 20150108959
    Abstract: A DC converter circuit having high reliability is provided. The DC converter circuit includes: an inductor configured to generate electromotive force in accordance with a change in flowing current; a transistor including a gate, a source, and a drain, which is configured to control generation of the electromotive force in the inductor by being on or off; a rectifier in a conducting state when the transistor is off; and a control circuit configured to control on and off of the transistor. The transistor includes an oxide semiconductor layer whose hydrogen concentration is less than or equal to 5×1019 atoms/cm3 as a channel formation layer.
    Type: Application
    Filed: December 23, 2014
    Publication date: April 23, 2015
    Inventors: Kei TAKAHASHI, Yoshiaki ITO, Hiroki INOUE, Tatsuji NISHIJIMA
  • Patent number: 9007813
    Abstract: A semiconductor device includes a plurality of memory cells including a first transistor and a second transistor, a reading circuit including an amplifier circuit and a switch element, and a refresh control circuit. A first channel formation region and a second channel formation region contain different materials as their respective main components. A first gate electrode is electrically connected to one of a second source electrode and a second drain electrode. The other of the second source electrode and the second drain electrode is electrically connected to one of input terminals of the amplifier circuit. An output terminal of the amplifier circuit is connected to the other of the second source electrode and the second drain electrode through the switch element. The refresh control circuit is configured to control whether the switch element is turned on or off.
    Type: Grant
    Filed: March 12, 2013
    Date of Patent: April 14, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Toshihiko Saito, Takanori Matsuzaki, Shuhei Nagatsuka, Hiroki Inoue
  • Patent number: 8988116
    Abstract: Provided is a method for driving a semiconductor device, which allows a reduction in scale of a circuit, reduce the power consumption, and increase the speed of reading data. An H level (data “1”) potential or an L level (data “0”) potential is written to a node of a memory cell. Potentials of a source line and a bit line are set to the same potential at an M level (L level<M level<H level) so that the potential of the node is held. When the potential of the bit line is maintained at the M level, data “1” is read and when the potential of the bit line is reduced to an L level, data “0” is read.
    Type: Grant
    Filed: December 20, 2012
    Date of Patent: March 24, 2015
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiroki Inoue, Tatsuya Onuki
  • Patent number: 8981107
    Abstract: There are provided a nitrogen-containing heterocyclic compound such as a substituted amino-pyridine-N-oxide compound represented by formula (1), which is useful as a synthetic intermediate for an agrochemical and the like; and a method for producing the nitrogen-containing heterocyclic compound. (In formula (1), R1 and R2 each represents a hydrogen atom or an unsubstituted or substituted alkyl group; R3 represents a hydrogen atom, an unsubstituted or substituted alkylcarbonyl group or the like; R4 represents an unsubstituted or substituted alkylcarbonyl group, an unsubstituted or substituted arylcarbonyl group or the like; A represents a hydroxyl group, a thiol group or the like; m represents any one of integers of 1 to 4; k represents any one of integers of 0 to 3; and k+m?4.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: March 17, 2015
    Assignee: Nippon Soda Co., Ltd.
    Inventors: Koichi Kutose, Hiroki Inoue, Shiro Tsubokura
  • Patent number: 8962849
    Abstract: There are provided a nitrogen-containing heterocyclic compound such as a substituted amino-pyridine-N-oxide compound represented by formula (1), which is useful as a synthetic intermediate for an agrochemical and the like; and a method for producing the nitrogen-containing heterocyclic compound. (In formula (1), R1 and R2 each represents a hydrogen atom or an unsubstituted or substituted alkyl group; R3 represents a hydrogen atom, an unsubstituted or substituted alkylcarbonyl group or the like; R4 represents an unsubstituted or substituted alkylcarbonyl group, an unsubstituted or substituted arylcarbonyl group or the like; A represents a hydroxyl group, a thiol group or the like; m represents any one of integers of 1 to 4; k represents any one of integers of 0 to 3; and k+m?4.).
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: February 24, 2015
    Assignee: Nippon Soda Co., Ltd.
    Inventors: Koichi Kutose, Hiroki Inoue, Shiro Tsubokura
  • Patent number: 8962850
    Abstract: There are provided a nitrogen-containing heterocyclic compound such as a substituted amino-pyridine-N-oxide compound represented by formula (1), which is useful as a synthetic intermediate for an agrochemical and the like; and a method for producing the nitrogen-containing heterocyclic compound. (In formula (1), R1 and R2 each represents a hydrogen atom or an unsubstituted or substituted alkyl group; R3 represents a hydrogen atom, an unsubstituted or substituted alkylcarbonyl group or the like; R4 represents an unsubstituted or substituted alkylcarbonyl group, an unsubstituted or substituted arylcarbonyl group or the like; A represents a hydroxyl group, a thiol group or the like; m represents any one of integers of 1 to 4; k represents any one of integers of 0 to 3; and k+m?4.
    Type: Grant
    Filed: February 7, 2014
    Date of Patent: February 24, 2015
    Assignee: Nippon Soda Co., Ltd.
    Inventors: Koichi Kutose, Hiroki Inoue, Shiro Tsubokura
  • Publication number: 20150025276
    Abstract: A method for producing an organolithium compound includes the step of reacting an aromatic compound or a halogenated unsaturated aliphatic compound and a lithiating agent in the presence of a coordinating compound containing three or more elements having a coordinating ability in a molecule, at least one thereof being a nitrogen element, or a coordinating compound containing three or more oxygen elements having a coordinating ability in a molecule, at least one of the groups containing the oxygen elements having a coordinating ability being a tertiary alkoxy group, at a temperature of ?40° C. to 40° C.
    Type: Application
    Filed: October 3, 2014
    Publication date: January 22, 2015
    Applicant: Nippon Soda Co., Ltd.
    Inventor: Hiroki Inoue
  • Patent number: 8922182
    Abstract: A DC converter circuit having high reliability is provided. The DC converter circuit includes: an inductor configured to generate electromotive force in accordance with a change in flowing current; a transistor including a gate, a source, and a drain, which is configured to control generation of the electromotive force in the inductor by being on or off; a rectifier in a conducting state when the transistor is off; and a control circuit configured to control on and off of the transistor. The transistor includes an oxide semiconductor layer whose hydrogen concentration is less than or equal to 5×1019 atoms/cm3 as a channel formation layer.
    Type: Grant
    Filed: November 30, 2010
    Date of Patent: December 30, 2014
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Kei Takahashi, Yoshiaki Ito, Hiroki Inoue, Tatsuji Nishijima
  • Patent number: 8908204
    Abstract: A method for transferring a package of files that is executed by a personal computer, the package of files being made up of plural compressed files that are separately present therein. For transferring the package of files, the personal computer creates, with respect to each printer, a dedicated file that is exclusively acceptable to similar-dedicated-file-compatible models of the printer; the personal computer treats the respective dedicated files as the plural files and creates the package of files by packaging the respective dedicated files in the package of files; and with respect to the respective dedicated files in the package of files, in transferring the package of files, when it is detected by the personal computer, that the personal computer is connected to the printer that is compatible with the dedicated file, the personal computer transfers the dedicated file in the package of files to the detected printer.
    Type: Grant
    Filed: February 11, 2011
    Date of Patent: December 9, 2014
    Assignee: Brother Kogyo Kabushiki Kaisha
    Inventors: Hiroki Inoue, Tetsuya Nose, Mina Kawai