Patents by Inventor Hiroki Kihara

Hiroki Kihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8246152
    Abstract: A liquid discharge head comprises an element substrate made of Si having a discharge port for discharging a liquid, an energy generating element for generating an energy for allowing the liquid to be discharged from the discharge port, and a supply port for supplying the liquid to the discharge port and a liquid containing member made of a resin having a communication port communicated with the supply port, in which the element substrate and the liquid containing member are adhered with an adhesive agent. An inorganic film obtained by hardening compositions containing a silica precursor is formed on at least a surface corresponding to a portion of the liquid containing member to which the element substrate is adhered.
    Type: Grant
    Filed: December 1, 2008
    Date of Patent: August 21, 2012
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroki Kihara, Akihiko Shimomura
  • Publication number: 20120120289
    Abstract: An image outputting apparatus includes a header production section for producing a header including header information formed from first and second frame information regarding whether pixel data included in a payload are of first and last lines of one frame, respectively, first line information regarding whether or not the pixel data included in the payload are valid, and second line information regarding a line number of a line formed from the pixel data included in the payload, and an error detection code for use for detection of an error of the header information. A packet production section produces a packet which includes, in the payload thereof, pixel data for one line which configure an image obtained by imaging by an imaging section and to which the header is added. An outputting section outputs the produced packet to an image processing apparatus.
    Type: Application
    Filed: September 23, 2011
    Publication date: May 17, 2012
    Applicant: Sony Corporation
    Inventors: Tatsuya SUGIOKA, Hiroshi Shiroshita, Miho Ozawa, Hiroki Kihara, Kenichi Maruko, Tatsuo Shinbashi, Kazuhisa Funamoto, Hideyuki Matsumoto, Takayuki Toyama, Hayato Wakabayashi, Naohiro Koshisaka, Shigetoshi Sasaki, Masato Tamori
  • Publication number: 20120120287
    Abstract: The present disclosure provides an image outputting apparatus, including, an image pickup section, an error correction code calculation section adapted to calculate an error correction code using pixel data, which configure an image obtained by image pickup by the image pickup section, as an information word, and an outputting section adapted to output coded data, which are data of a codeword obtained by adding the error correction code to the pixel data, to an image processing apparatus provided in an apparatus in which the image outputting apparatus is provided.
    Type: Application
    Filed: October 20, 2011
    Publication date: May 17, 2012
    Applicant: Sony Corporation
    Inventors: Kazuhisa FUNAMOTO, Tatsuo Shinbashi, Hideyuki Matsumoto, Hiroshi Shiroshita, Hiroki Kihara, Kenichi Maruko, Tatsuya Sugioka, Naohiro Koshisaka, Shigetoshi Sasaki, Masato Tamori, Takayuki Toyama, Miho Ozawa, Hayato Wakabayashi
  • Patent number: 8125278
    Abstract: Disclosed herein is a clock regeneration apparatus, including: an oscillator including n (an integer of two or more) gating groups connected in cascade connection to each other forming an oscillation loop, the gating groups being controlled to gate an internal clock signal with first to nth gating signals different from one another, respectively, the oscillator outputting a clock signal at least from the nth one of the gating groups; an edge detection section adapted to detect an edge of a reception data signal; a phase decision section adapted to decide a phase of the clock signal for each edge of the reception data signal and output a result of the decision as a phase decision signal; and a gating signal generation section adapted to generate the first to nth gating signals and output the gating signals to first to nth ones of the gating groups, respectively.
    Type: Grant
    Filed: April 21, 2010
    Date of Patent: February 28, 2012
    Assignee: Sony Corporation
    Inventors: Kenichi Maruko, Hiroki Kihara
  • Publication number: 20110279546
    Abstract: Provided is a liquid ejection head, comprising a chip having a liquid ejection pressure generating element and an electrode terminal for electrically connecting the liquid ejection pressure generating element to an outside, an electrical wiring board having a lead wiring to be electrically connected to the electrode terminal, and a lead sealing material for covering an electrical connection portion between the electrode terminal and the lead wiring. The lead sealing material contains an epoxy resin (a) which has an average number of functional groups per molecule of more than two and is solid at 25° C., an acid anhydride curing agent (b) having a polybutadiene backbone, a curing accelerator (c), and an inorganic filler (d).
    Type: Application
    Filed: April 8, 2011
    Publication date: November 17, 2011
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroki Kihara, Tadayoshi Inamoto, Isao Imamura, Yoshihiro Hamada
  • Patent number: 7952520
    Abstract: A monitor antenna receives radio waves transmitted from a Doppler very high frequency omnidirectional radio range (DVOR) device and includes a carrier signal and a subcarrier signal, orthogonal detectors shift a phase of a signal of each subcarrier component by a phase difference equivalent to a prescribed distance away from the DVOR apparatus relative to a signal of a carrier component, and a combiner combines signals of the carrier component and the subcarrier component to output the combined signal to a DVOR demodulator.
    Type: Grant
    Filed: August 31, 2007
    Date of Patent: May 31, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroki Kihara
  • Publication number: 20100315462
    Abstract: A liquid discharge head includes a substrate having, on one side thereof, energy generating elements for generating energy used for discharging liquid, and a sealing member arranged in contact with at least a part of one or more end faces of the substrate, the sealing member being a cured product of a composition having an epoxy resin having a butadiene skeleton and an epoxy resin curing agent having a butadiene skeleton.
    Type: Application
    Filed: June 11, 2010
    Publication date: December 16, 2010
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Isao Imamura, Tadayoshi Inamoto, Akane Hisanaga, Hiroki Kihara
  • Publication number: 20100301950
    Abstract: Disclosed herein is a clock regeneration apparatus, including: an oscillator including n (an integer of two or more) gating groups connected in cascade connection to each other forming an oscillation loop, the gating groups being controlled to gate an internal clock signal with first to nth gating signals different from one another, respectively, the oscillator outputting a clock signal at least from the nth one of the gating groups; an edge detection section adapted to detect an edge of a reception data signal; a phase decision section adapted to decide a phase of the clock signal for each edge of the reception data signal and output a result of the decision as a phase decision signal; and a gating signal generation section adapted to generate the first to nth gating signals and output the gating signals to first to nth ones of the gating groups, respectively.
    Type: Application
    Filed: April 21, 2010
    Publication date: December 2, 2010
    Applicant: Sony Corporation
    Inventors: Kenichi Maruko, Hiroki Kihara
  • Patent number: 7791531
    Abstract: A VOR monitoring receiving apparatus includes a receiving circuit for receiving a field signal from a VOR apparatus, and outputting content of the field signal to a plurality of signal systems, first and second monitoring receiving circuits provided in first and second signal systems included in the plurality of signal systems, respectively, for monitoring the content of the field signal, a self-check signal generator for generating a self-check signal necessary to confirm whether the first and second monitoring receiving circuits normally operate, a VOR monitoring controller for detecting an abnormality of the VOR apparatus based on monitoring results of the first and second monitoring receiving circuits, a switch for performing switching to alternately output the field signal and the self-check signal to the first and second signal systems, and a switch controller for controlling the switch to perform switching whenever a preset time elapses.
    Type: Grant
    Filed: January 24, 2008
    Date of Patent: September 7, 2010
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroki Kihara
  • Patent number: 7760843
    Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
    Type: Grant
    Filed: August 7, 2008
    Date of Patent: July 20, 2010
    Assignee: International Business Machines Corporation
    Inventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
  • Patent number: 7600857
    Abstract: A liquid discharge head includes a discharge element substrate including an energy generating element that generates energy for discharging liquid, a discharge port provided so as to correspond to the energy generating element, and a supply path for supplying the liquid to the discharge port. The discharge element substrate has an open face to which the discharge port is open, a back face of the open face, and side faces formed between the open face and the back face, and at least a part of the side faces is sealed by a sealing agent, which contains a filler made of fluororesin.
    Type: Grant
    Filed: December 14, 2006
    Date of Patent: October 13, 2009
    Assignee: Canon Kabushiki Kaisha
    Inventors: Hiroki Kihara, Akihiko Shimomura, Tadayoshi Inamoto
  • Publication number: 20090232250
    Abstract: A communication system includes: a transmitter adapted to transmit a synchronizing clock and serial data synchronous with the synchronizing clock over a line at low amplitude; and a receiver adapted to receive the serial data and synchronizing clock from the transmitter. The receiver includes an amplifier adapted to amplify the received synchronizing clock of low amplitude to restore the clock to its original amplitude, a latched comparator adapted to latch the received serial data in synchronism with a reproduction clock, and a phase-locked circuit.
    Type: Application
    Filed: March 11, 2009
    Publication date: September 17, 2009
    Inventors: Takaaki YAMADA, Hiroki KIHARA, Tatsuya SUGIOKA, Hisashi OWA, Taichi NIKI, Yukio SHIMOMURA
  • Publication number: 20090174602
    Abstract: A monitor antenna receives radio waves transmitted from a Doppler very high frequency omnidirectional radio range (DVOR) device and includes a carrier signal and a subcarrier signal, orthogonal detectors shift a phase of a signal of each subcarrier component by a phase difference equivalent to a prescribed distance away from the DVOR apparatus relative to a signal of a carrier component, and a combiner combines signals of the carrier component and the subcarrier component to output the combined signal to a DVOR demodulator.
    Type: Application
    Filed: August 31, 2007
    Publication date: July 9, 2009
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroki Kihara
  • Publication number: 20090141085
    Abstract: A liquid discharge head comprises an element substrate made of Si having a discharge port for discharging a liquid, an energy generating element for generating an energy for allowing the liquid to be discharged from the discharge port, and a supply port for supplying the liquid to the discharge port and a liquid containing member made of a resin having a communication port communicated with the supply port, in which the element substrate and the liquid containing member are adhered with an adhesive agent. An inorganic film obtained by hardening compositions containing a silica precursor is formed on at least a surface corresponding to a portion of the liquid containing member to which the element substrate is adhered.
    Type: Application
    Filed: December 1, 2008
    Publication date: June 4, 2009
    Applicant: CANON KABUSHIKI KAISHA
    Inventors: Hiroki Kihara, Akihiko Shimomura
  • Patent number: 7535020
    Abstract: Systems and methods for positioning thermal sensors within an integrated circuit in a manner that provides useful thermal measurements corresponding to different parts of the integrated circuit. In one embodiment, an integrated circuit includes multiple, duplicate functional blocks. A separate thermal sensor is coupled to each of the duplicate functional blocks, preferably in the same relative location on each of the duplicate functional blocks, and preferably at a hotspot. One embodiment also includes thermal sensors on one or more functional blocks of other types in the integrated circuit. One embodiment includes a thermal sensor positioned at a cool spot, such as at the edge of the integrated circuit chip. Each of the thermal sensors may have ports to enable power and ground connections or data connections between the sensors and external components or devices.
    Type: Grant
    Filed: June 28, 2005
    Date of Patent: May 19, 2009
    Assignees: Kabushiki Kaisha Toshiba, International Business Machines Corporation, Sony Computer Entertainment Inc.
    Inventors: Munehiro Yoshida, Daniel Stasiak, Michael F. Wang, Charles R. Johns, Hiroki Kihara, Tetsuji Tamura, Kazuaki Yazawa, Iwao Takiguchi
  • Publication number: 20090121919
    Abstract: A VOR monitoring receiving apparatus includes a receiving circuit for receiving a field signal from a VOR apparatus, and outputting content of the field signal to a plurality of signal systems, first and second monitoring receiving circuits provided in first and second signal systems included in the plurality of signal systems, respectively, for monitoring the content of the field signal, a self-check signal generator for generating a self-check signal necessary to confirm whether the first and second monitoring receiving circuits normally operate, a VOR monitoring controller for detecting an abnormality of the VOR apparatus based on monitoring results of the first and second monitoring receiving circuits, a switch for performing switching to alternately output the field signal and the self-check signal to the first and second signal systems, and a switch controller for controlling the switch to perform switching whenever a preset time elapses.
    Type: Application
    Filed: January 24, 2008
    Publication date: May 14, 2009
    Inventor: Hiroki KIHARA
  • Publication number: 20080301503
    Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
    Type: Application
    Filed: August 7, 2008
    Publication date: December 4, 2008
    Inventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
  • Patent number: 7453293
    Abstract: The present invention provides for a self-correcting state circuit. A first flip flop is configured to receive a clock input and a first data input, and to generate a first output in response to the clock input and the first data input. A second flip flop is coupled to the first flip flop and configured to receive the clock input and to receive the first output as a second data input, and to generate a second output in response to the clock input and the first output. A first correction circuit is coupled to the second flip flop and configured to generate a corrected output. A third flip flop is coupled to the first correction circuit and configured to receive the clock input and to receive the corrected output as a third data input, and to generate a third output in response to the clock input and the third data input.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: November 18, 2008
    Assignee: International Business Machines Corporation
    Inventors: David William Boerstler, Eric John Lukes, Hiroki Kihara, James David Strom
  • Publication number: 20080133989
    Abstract: Methods and apparatus for dynamically (AC) testing a target circuit within a main circuit include: providing respective sets of input latches from among a plurality of latches of the main circuit; reconfiguring connections of at least some of the input latches from normal connections within the main circuit such that each set of input latches is connected in series and directs an input bit stream from an associated source node into an associated input node of the target circuit; scanning a plurality of sets of input bits into the respective sets of input latches such that each latch of each set of input latches contains a respective bit of an associated one of the sets of input bits; and scanning each of the sets of input bits serially into the respective input nodes of the target circuit at a sufficiently high frequency to dynamically test the target circuit.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Applicant: Sony Computer Entertainment Inc.
    Inventors: Atsushi Hayashi, Chiaki Takano, Noriyuki Oshima, Takeshi Inoue, Hiroki Kihara, Yoichi Nishino
  • Publication number: 20070139467
    Abstract: A liquid discharge head includes a discharge element substrate including an energy generating element that generates energy for discharging liquid, a discharge port provided so as to correspond to the energy generating element, and a supply path for supplying the liquid to the discharge port, wherein the discharge element substrate has an open face to which the discharge port is open, a back face of the open face, and side faces formed between the open face and the back face, and at least a part of the side faces is sealed by a sealing agent, wherein the sealing agent contains filler made of fluororesin.
    Type: Application
    Filed: December 14, 2006
    Publication date: June 21, 2007
    Applicant: Canon Kabushiki Kaisha
    Inventors: Hiroki Kihara, Akihiko Shimomura, Tadayoshi Inamoto