Patents by Inventor Hiroki Mouri
Hiroki Mouri has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240092421Abstract: A steering device and a method for controlling the steering device according to the present invention are capable of suppressing, in a steer-by-wire steering device including a steering operation input member and a turning actuator that applies a turning force to a road wheel based on a driving signal, a change in which a yaw rate gain of a vehicle rises with respect to the operation speed of the steering operation input member by changing a turning angle command value to an angle less than the angle before the change when a turning frequency of the road wheel is a predetermined frequency. As a result, it becomes possible to suppress a case in which the yaw rate gain of the vehicle becomes too sensitive with respect to a steering operation by a driver.Type: ApplicationFiled: December 28, 2021Publication date: March 21, 2024Applicants: HITACHI ASTEMO, LTD., National University Corporation Tokyo University of Agriculture and TechnologyInventors: Hiroki SONODA, Yoshiji HASEGAWA, Tomoaki FUJlBAYASHI, Hiroshi MOURI
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Patent number: 8897350Abstract: A phase adjuster arranges phases of waveforms of a complex signal after orthogonal transform. An edge detector detects an edge of the complex signal after phase adjustment. A phase shift detector detects phase shift of an output signal of the edge detector between the in-phase signal and the quadrature signal after the orthogonal transform, and outputs a phase error signal (PE). The oscillator connected to mixers and a shifter to perform the orthogonal transform includes a phase adjustment section adjusting an edge of a voltage controlled oscillator (VCO) clock based on the phase error signal (PE) and correcting the phase shift of an original signal.Type: GrantFiled: June 19, 2014Date of Patent: November 25, 2014Assignee: Panasonic CorporationInventors: Hiroki Mouri, Kouichi Nagano, Hiroyuki Tezuka
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Publication number: 20140301516Abstract: A phase adjuster arranges phases of waveforms of a complex signal after orthogonal transform. An edge detector detects an edge of the complex signal after phase adjustment. A phase shift detector detects phase shift of an output signal of the edge detector between the in-phase signal and the quadrature signal after the orthogonal transform, and outputs a phase error signal (PE). The oscillator connected to mixers and a shifter to perform the orthogonal transform includes a phase adjustment section adjusting an edge of a voltage controlled oscillator (VCO) clock based on the phase error signal (PE) and correcting the phase shift of an original signal.Type: ApplicationFiled: June 19, 2014Publication date: October 9, 2014Inventors: Hiroki MOURI, Kouichi NAGANO, Hiroyuki TEZUKA
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Patent number: 8648632Abstract: In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.Type: GrantFiled: December 7, 2011Date of Patent: February 11, 2014Assignee: Panasonic CorporationInventors: Hiroki Mouri, Kouji Okamoto, Fumiaki Senoue
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Patent number: 8270269Abstract: An asynchronous timing detector 3 detects and measures a specific pattern (sync pattern) of audio and video reproduced signals having a digital value form an A/D converter 2 and its appearance interval based on an asynchronous clock generated by an asynchronous clock generator 4, and calculates a cycle ratio of the measured sync pattern appearance interval (the number of clock pulses of the asynchronous clock) to a normal value (the number of clock pulses of a synchronous clock obtained by measuring a sync pattern appearance interval using the synchronous clock). A pseudo-synchronous clock generator 7 thins the asynchronous clock based on the cycle ratio to generate a pseudo-synchronous clock which is pseudo-synchronous with channel data. Therefore, even when an initial frequency error is large, frequency and phase pull-in is relatively quickly performed until a timing recovery operation becomes stable.Type: GrantFiled: November 11, 2005Date of Patent: September 18, 2012Assignee: Panasonic CorporationInventors: Hiroki Mouri, Akira Yamamoto
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Publication number: 20120081339Abstract: In a digital PLL circuit, a phase comparison circuit counts the numbers of transitions of a reference clock and an oscillation clock, sets a time taken until the number of transitions of the reference clock reaches a reference count value as a phase comparison time period, and detects, as a phase error value, a difference between a target count value, obtained based on a magnification value of a desired oscillating frequency with respect to the frequency of the reference clock and the reference count value, and the number of transitions of the oscillation clock in the phase comparison time period. A smoothing circuit smoothes the phase error value. A digitally-controlled oscillation circuit controls the frequency of the oscillation clock in accordance with the phase error value smoothed by the smoothing circuit.Type: ApplicationFiled: December 7, 2011Publication date: April 5, 2012Applicant: PANASONIC CORPORATIONInventors: Hiroki MOURI, Kouji Okamoto, Fumiaki Senoue
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Patent number: 8098972Abstract: In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.Type: GrantFiled: November 1, 2007Date of Patent: January 17, 2012Assignee: Panasonic CorporationInventors: Kouji Okamoto, Akira Yamamoto, Hiroki Mouri, Yoshinori Shirakawa
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Publication number: 20110095786Abstract: In a phase comparator used for a sync clock extraction circuit for extracting a clock synchronizing with reproduction data, a zero cross detection section 701, receiving the reproduction data, outputs a rising cross detection signal, a falling cross detection signal and three phase error candidates that are three consecutive samples. Rising and falling reference value hold sections 703 and 704 respectively output rising and falling reference values. When receiving the rising or falling cross detection signal, a phase error calculation section 702 outputs a sample the difference of which from the rising or falling reference value is minimum in absolute value, out of the three samples including a zero cross sample, as a phase error. The phase error is held in the rising or falling reference value hold section 703 or 704 as the rising or falling reference value for the next phase error calculation.Type: ApplicationFiled: September 22, 2008Publication date: April 28, 2011Inventors: Akira Yamamoto, Yoshinori Shirakawa, Kouji Okamoto, Hiroki Mouri
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Patent number: 7898451Abstract: A plurality of comparators (CMP1, CMP2, . . . ) respectively correspond to a plurality of reference voltages (V1, V2, . . . ), and each compares a reference voltage corresponding to the comparator with a signal level of an analog signal (Sin). An encoder (102) generates a digital signal (De) corresponding to the analog signal (Sin) based on outputs (S1, S2, . . . ) of the plurality of comparators. A pattern detection circuit (103) detects that a temporal change of an output (S3) of a first comparator matches a predetermined first particular pattern. A control circuit (104) corrects a digital value of the digital signal (De) in response to detection by the pattern detection circuit. The temporal change of the output (S3) of the first comparator becomes the first particular pattern when an amplitude of the analog signal (Sin) is smaller than a predetermined amplitude.Type: GrantFiled: February 10, 2009Date of Patent: March 1, 2011Assignee: Panasonic CorporationInventors: Hiroki Mouri, Kouichi Nagano
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Publication number: 20100194618Abstract: A plurality of comparators (CMP1, CMP2, . . . ) respectively correspond to a plurality of reference voltages (V1, V2, . . . ), and each compares a reference voltage corresponding to the comparator-with a signal level of an analog signal (Sin). An encoder (102) generates a digital signal (De) corresponding to the analog signal (Sin) based on outputs (S1, S2, . . . ) of the plurality of comparators. A pattern detection circuit (103) detects that a temporal change of an output (S3) of a first comparator matches a predetermined first particular pattern. A control circuit (104) corrects a digital value of the digital signal (De) in response to detection by the pattern detection circuit. The temporal change of the output (S3) of the first comparator becomes the first particular pattern when an amplitude of the analog signal (Sin) is smaller than a predetermined amplitude.Type: ApplicationFiled: February 10, 2009Publication date: August 5, 2010Applicant: PANASONIC CORPORATIONInventors: Hiroki Mouri, Kouichi Nagano
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Patent number: 7688687Abstract: In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.Type: GrantFiled: July 18, 2006Date of Patent: March 30, 2010Assignee: Panasonic CorporationInventors: Kouji Okamoto, Akira Yamamoto, Hiroki Mouri
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Publication number: 20100066722Abstract: In an asynchronous read channel system, a reference value interpolation-type maximum likelihood decoder ASML having a small circuit scale (e.g., seven taps) is employed. A nonlinear waveform the equalizer SEQ is provided before the maximum likelihood decoder ASML. The nonlinear waveform the equalizer SEQ includes an FIR filter having, for example, four taps, and performs nonlinear waveform equalization with respect to an input digital signal so that only signal components having small amplitudes and high frequencies are amplified. After the nonlinear waveform equalization, the signal is input to the reference value interpolation-type maximum likelihood decoder ASML, which performs maximum likelihood decoding with respect to the signal. Therefore, even when the reference value interpolation-type maximum likelihood decoder includes a smaller number of taps and thus has a small circuit scale, maximum likelihood decoding with a high error correction function can be performed.Type: ApplicationFiled: November 13, 2007Publication date: March 18, 2010Inventor: Hiroki Mouri
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Publication number: 20100020250Abstract: In a feedforward control type reproduced signal processor, a clock generator 1 changes a clock frequency, depending on a digital value set by a digital value generator 7. Therefore, power consumption of a system is optimized and control is facilitated. Moreover, when a frequency lock state is established in which a frequency ratio calculated by a frequency ratio calculator 3 satisfies a set condition, a modulation component having a small change is generated using a clock of a clock generator 1. Therefore, the digital value is updated with the modulation component, so that a change in clock frequency of the clock generator 1 gradually varies. As a result, the influence of the change in clock frequency on the response of a decoding process is reduced.Type: ApplicationFiled: November 1, 2007Publication date: January 28, 2010Inventors: Kouji Okamoto, Akira Yamamoto, Hiroki Mouri, Yoshinori Shirakawa
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Patent number: 7523154Abstract: A write compensation circuit of a recording device includes a first delay portion driven by a first driving voltage, for receiving a clock signal, delaying the clock signal by a first delay time, and outputting the delayed clock signal, and a voltage supplying portion for supplying the first driving voltage to the first delay portion in such a manner that the first delay time is substantially equal to a clock period of the clock signal.Type: GrantFiled: August 8, 2005Date of Patent: April 21, 2009Assignee: Panasonic CorporationInventors: Hirokuni Fujiyama, Shiro Dosho, Hiroyuki Nakahira, Akira Yamamoto, Hiroki Mouri
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Publication number: 20090086588Abstract: In a feedforward timing extractor for extracting timing information from a playback signal, a frequency ratio calculation section 2 calculates the ratio between the frequency of the playback signal and the frequency of the output clock of a frequency synthesizer 6 by utilizing a specific pattern and a specific pattern appearing interval in the playback signal. A control section 4 controls the frequency dividing rate of the frequency synthesizer 6 in such a manner that the frequency ratio calculated by the frequency ratio calculation section 2 has a set value. Thus, as compared with a case in which the output clock of the frequency synthesizer 6 is a high-frequency fixed-rate clock, it is not necessary to operate the digital circuits at high speeds. Consequently, even in cases where the playback frequency (the playback rate) of the signal changes with time, the decimation rate at which pulses of a fixed clock are eliminated is constant, thereby reducing power consumption.Type: ApplicationFiled: July 18, 2006Publication date: April 2, 2009Inventors: Kouji Okamoto, Akira Yamamoto, Hiroki Mouri
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Publication number: 20090060451Abstract: An asynchronous timing detector 3 detects and measures a specific pattern (sync pattern) of audio and video reproduced signals having a digital value form an A/D converter 2 and its appearance interval based on an asynchronous clock generated by an asynchronous clock generator 4, and calculates a cycle ratio of the measured sync pattern appearance interval (the number of clock pulses of the asynchronous clock) to a normal value (the number of clock pulses of a synchronous clock obtained by measuring a sync pattern appearance interval using the synchronous clock). A pseudo-synchronous clock generator 7 thins the asynchronous clock based on the cycle ratio to generate a pseudo-synchronous clock which is pseudo-synchronous with channel data. Therefore, even when an initial frequency error is large, frequency and phase pull-in is relatively quickly performed until a timing recovery operation becomes stable.Type: ApplicationFiled: November 11, 2005Publication date: March 5, 2009Inventors: Hiroki Mouri, Akira Yamamoto
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Publication number: 20080253011Abstract: There is provided a signal processing apparatus and a signal processing method, which can simultaneously perform reduction in jitter components and reduction in error rate. A signal processing apparatus for processing a signal by a PRML method is provided with an A/D converter (4) for converting an analog signal into a digital signal; a first waveform equalizer (14) which is connected to the A/D converter (4), and amplifies a specific band of a signal to optimize data of a clock extraction system; a second waveform equalizer (15) which is connected to the A/D converter (4), and amplifies the specific band of the signal and performs waveform equalization to optimize data of a data processing system; a timing recovery logic circuit (11) which is connected to the first waveform equalizer (14), and extracts a reproduction clock; and a decoder (16) which is connected to the second waveform equalizer (15), and decodes data.Type: ApplicationFiled: January 6, 2005Publication date: October 16, 2008Applicant: Matusuhita Electric Industrial Co., Ltd.Inventors: Hiroki Mouri, Akira Yamamoto
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Publication number: 20080101176Abstract: There has been an issue that the operation of a semiconductor circuit performing edge timing control cannot follow up in the multipulse generation process where high multiplication of speed progresses every year. A light strategy drive comprises a control register (22) storing timing edge information for generating the edge of a recording waveform signal, a PLL (23) generating a clock for generating the edge of a recording waveform signal, and a timing control circuit (24) for receiving timing edge information corresponding to the recording waveform signal from the control register (22) to output timing edge information having a predetermined amount of delay in parallel and compounding the edges based on the timing edge information outputted in parallel. Timing edge can be controlled with high precision even at the time of high speed operation, and a high precision multipulse can be generated.Type: ApplicationFiled: October 20, 2005Publication date: May 1, 2008Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroki Mouri, Hiroyuki Nakahira, Kouichi Nagano
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Patent number: 7327658Abstract: The present invention is made to improve the conventional analog processing that is easily affected by variations in semiconductor processing. This invention provides a wobble signal processing apparatus that can reduce the circuit scale and the power consumption as well as improve the quality of signal processing. The wobble signal processing apparatus of the present invention digitally processes a part that has conventionally been processed by an analog system, and a PRML circuit is further provided to implement error detection, whereby the circuit scale and the power consumption is reduced. This improves the detection of a signal that is inputted to the wobble signal processing apparatus.Type: GrantFiled: November 28, 2003Date of Patent: February 5, 2008Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroki Mouri, Kouji Okamoto, Youichi Ogura
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Patent number: 7068584Abstract: The signal processor includes an analog filter, an analog-to-digital (A-D) converter, an adaptive equalization filter, a quality value calculating circuit, and a control circuit. The analog filter removes high-frequency noises of a played-back signal from a recording medium and amplifies a specific frequency band of the played-back signal. The A-D converter converts the played-back signal from the analog filter into a digital signal. The adaptive equalization filter performs waveform equalization of the played-back signal from the A-D converter while adjusting a tap coefficient of the adaptive equalization filter so as to reduce a difference between an output of the adaptive equalization filter and a target value. The quality value calculating circuit calculates a quality value based on the difference between the output of the adaptive equalization filter and the target value.Type: GrantFiled: March 3, 2003Date of Patent: June 27, 2006Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroki Mouri, Hiroyuki Nakahira, Akira Yamamoto