Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.

Abstract: A resin-coated metal sheet for can lids includes a metal sheet coated with thermoplastic resin films on both surfaces and formed into a can lid. A thermoplastic resin film A based on polybutylene terephthalate (PBT) and polyethylene terephthalate (PET) is heat-fused on a surface of the metal sheet serving as an exterior surface of the can lid, and a thermoplastic resin film B based on polyethylene terephthalate (PET) is heat-fused on a surface of the metal sheet serving as an interior surface of the can lid. A composition ratio (wt %) of PBT/PET in the thermoplastic resin film A on the exterior surface is (PBT/PET)=(40/60) to (80/20), and the thermoplastic resin film B on the interior surface includes 95 mol % or more of PET.

Abstract: A semiconductor device includes a planar semiconductor layer formed on a substrate; a pillar-shaped semiconductor layer formed on the planar semiconductor layer; a gate insulating film surrounding the pillar-shaped semiconductor layer; a first metal surrounding the gate insulating film, the first metal being in contact with an upper portion of the planar semiconductor layer; a gate formed above the first metal so as to surround the gate insulating film, the gate being electrically insulated from the first metal; and a second metal formed above the gate so as to surround the gate insulating film, the second metal being electrically insulated from the gate, the second metal having an upper portion electrically connected to an upper portion of the pillar-shaped semiconductor layer.

Abstract: A semiconductor device includes a pillar-shaped semiconductor layer formed on a substrate; a first insulator surrounding the pillar-shaped semiconductor layer; a first gate surrounding the first insulator and made of a metal having a first work function; a second gate surrounding the first insulator and made of a metal having a second work function different from the first work function, the second gate being located below the first gate; a third gate surrounding the first insulator and made of a metal having the first work function, the third gate being located below the second gate; and a fourth gate surrounding the first insulator and made of a metal having the second work function different from the first work function, the fourth gate being located below the third gate. The first gate, the second gate, the third gate, and the fourth gate are electrically connected together.

Abstract: The method for producing a pillar-shaped semiconductor device includes a step of forming a tubular SiO2 layer that surrounds side surfaces of a P+ layer 38a and N+ layers 38b and 8c formed on a Si pillar 6b by epitaxial crystal growth, forming an AlO layer 51 on a periphery of the SiO2 layer, forming a tubular contact hole by etching the tubular SiO2 layer using the AlO layer 51 as a mask, and filling the contact hole with W layers 52c, 52d, and 52e to form tubular W layers 52c, 52d, and 52e (including a buffer conductor layer) that have an equal width when viewed in plan and are in contact with side surfaces of the tops of the P+ layer 38a and the N+ layers 38b and 8c.

Abstract: A method for producing a semiconductor device includes depositing a first oxide insulating film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate; depositing a sixth insulating nitride film; depositing a second oxide insulating film containing an impurity of the first conductivity type; depositing a seventh insulating nitride film; depositing a third oxide insulating film containing an impurity of the first conductivity type; etching the first insulating film, the sixth insulating film, the second insulating film, and the seventh insulating film to form a contact hole; forming a first pillar-shaped silicon layer in the contact hole by epitaxial growth; removing the sixth insulating film and the seventh insulating film; forming a first gate and a second gate; and forming a contact connecting the first gate and the second gate.

Abstract: In an SRAM cell circuit, an N+ layer 12a and a P+ layer 13a, which are present between first gate connection W layers 22a and 22b connecting to gate TiN layers 23a and 23b in plan view, which connect to the bottom portions of Si pillars 11a and 11b, and which extend in the horizontal direction, connect through a second gate connection W layer 29a to a first gate connection W layer 22c, which connects to the gate TiN layers 23a and 23b and extend in the horizontal direction. The second gate connection W layer 29a has a bottom portion within the first gate connection W layer 22c, and has an upper surface positioned lower than the upper surfaces of the gate TiN layers 23a to 23f and the first gate connection W layers 22a to 22d.

Abstract: A method for producing a semiconductor device includes depositing a first oxide insulating film containing an impurity of a first conductivity type on a fourth first-conductivity-type semiconductor layer formed on a substrate; depositing a sixth insulating nitride film; depositing a second oxide insulating film containing an impurity of the first conductivity type; depositing a seventh insulating nitride film; depositing a third oxide insulating film containing an impurity of the first conductivity type; etching the first insulating film, the sixth insulating film, the second insulating film, and the seventh insulating film to form a contact hole; forming a first pillar-shaped silicon layer in the contact hole by epitaxial growth; removing the sixth insulating film and the seventh insulating film; forming a first gate and a second gate; and forming a contact connecting the first gate and the second gate.

Abstract: A retention material for a gas processing device including a processing structure and a casing for accommodating the processing structure, the retention material including inorganic fibers and being arranged between the processing structure and the casing, wherein in a test of repeating a cycle of compressing the retention material until a bulk density of the retention material becomes a prescribed compression bulk density, followed by retaining for 10 seconds, and then releasing until a bulk density of the retention material becomes a release bulk density that is smaller by 12% of said prescribed compression bulk density; a release surface pressure of the retention material after repeating the cycle 2500 times and the compression bulk density of the retention material satisfies the relationship, P?17.10×D?1.62 wherein P is the release surface pressure (N/cm2) and D is the compression bulk density (g/cm3).

Abstract: A semiconductor device includes a first pillar-shaped semiconductor layer formed on a semiconductor substrate; a first first-conductivity-type semiconductor layer formed in the first pillar-shaped semiconductor layer; a third first-conductivity-type semiconductor layer formed in the first pillar-shaped semiconductor layer and located at a higher position than the first first-conductivity-type semiconductor layer; a first gate insulating film formed so as to surround a region of the first pillar-shaped semiconductor layer sandwiched between the first first-conductivity-type semiconductor layer and the third first-conductivity-type semiconductor layer; a first gate formed so as to surround the first gate insulating film; a second gate insulating film formed so as to surround a region of the first pillar-shaped semiconductor layer sandwiched between the first first-conductivity-type semiconductor layer and the third first-conductivity-type semiconductor layer; and a second gate formed so as to surround the secon

Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; and a second step following the first step and including forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to conduct planarization, forming a second resist for forming a gate line and a pillar-shaped semiconductor layer so that the second resist extends in a direction perpendicular to a direction in which the fin-shaped semiconductor layer extends, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form a pillar-shaped semiconductor layer and a first dummy gate formed of the first polysilicon.

Abstract: A holding material includes a stack of a first mat and a second mat, the first mat including alumina fibers that include 60 wt % or more of alumina and 40 wt % or less of silica, and the second mat including silica fibers that include 60 wt % or more of silica and 40 wt % or less of alumina and having a surface pressure higher than that of the first mat as measured at a gap bulk density of 0.30 g/cm3.

Abstract: A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.

Abstract: A method for producing a semiconductor device includes forming a fin-shaped semiconductor layer on a substrate, forming a first insulating film around the fin-shaped semiconductor layer, and a first metal film is formed around the first insulating film. A pillar-shaped semiconductor layer is formed on the fin-shaped semiconductor layer and a gate insulating film is formed around the pillar-shaped semiconductor layer. A gate electrode is formed around the gate insulating film, the gate electrode being made of a third metal, and a gate line is connected to the gate electrode. A second insulating film is formed around a sidewall of an upper portion of the pillar-shaped semiconductor layer, and a second metal film is formed around the second insulating film.

Abstract: A semiconductor device includes a fin-shaped semiconductor layer and a pillar-shaped semiconductor layer on the fin-shaped semiconductor layer. A metal gate line is connected to a metal gate electrode and extends in a direction perpendicular to a direction that of the fin-shaped semiconductor layer. A width of a bottom of the pillar-shaped semiconductor layer in a direction parallel to a direction in which the metal gate line extends is equal to a width of a top of the fin-shaped semiconductor layer in the direction parallel to the direction of the metal gate line. A gate insulating film is in contact with an underside of the gate electrode and the gate line and separates the metal gate electrode and the metal gate line from the fin-shaped semiconductor layer and a first insulating film. An outer width of the metal gate electrode is equal to a width of the metal gate line.

Abstract: A method for producing a memory device includes depositing a second interlayer insulating film on a substrate, forming contact holes, and depositing a second metal and a nitride film. The second metal and the nitride film are removed to form pillar-shaped nitride layers, and to form lower electrodes surrounding the pillar-shaped nitride layers. The second interlayer insulating film is etched back to expose upper portions of the lower electrodes. The upper portions of the lower electrodes surrounding the pillar-shaped nitride film are removed and a phase change film is deposited to surround the pillar-shaped nitride film and connect with the lower electrodes. The phase change film is etched on upper portions of the pillar-shaped nitride film, and a reset gate insulating film is formed surrounding the phase change film and forming a reset gate having a side wall shape and remaining on the upper portions of the pillar-shaped nitride film.

Abstract: A semiconductor device includes a first pillar-shaped semiconductor layer in which a second first-conductivity-type semiconductor layer, a first body region, a third first-conductivity-type semiconductor layer, a fourth first-conductivity-type semiconductor layer, a second body region, a fifth first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a third body region, and a second second-conductivity-type semiconductor layer are formed from a substrate side in this order; first, second, and third gates formed around first, second, third gate insulating films formed around the first, second, and third body regions, respectively; a first output terminal connecting the fifth first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer; a second pillar-shaped semiconductor layer, on the first output terminal, in which a third second-conductivity-type semiconductor layer, a fourth body region, and a fourth second-conductivity-typ