Patents by Inventor Hiroki Nakamura

Hiroki Nakamura has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180175047
    Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.
    Type: Application
    Filed: February 15, 2018
    Publication date: June 21, 2018
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 10002934
    Abstract: A semiconductor device includes a first planar semiconductor (e.g., silicon) layer, first and second pillar-shaped semiconductor (e.g., silicon) layers, a first gate insulating film, a first gate electrode, a second gate insulating film, a second gate electrode, a first gate line connected to the first and second gate electrodes, a first n-type diffusion layer, a second n-type diffusion layer, a first p-type diffusion layer, and a second p-type diffusion layer. A center line extending along the first gate line is offset by a first predetermined amount from a line connecting a center of the first pillar-shaped semiconductor layer and a center of the second pillar-shaped semiconductor layer.
    Type: Grant
    Filed: January 22, 2015
    Date of Patent: June 19, 2018
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Nozomu Harada, Hiroki Nakamura
  • Patent number: 10002963
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer, a first insulating film around the fin-shaped semiconductor layer, and a first metal film around the first insulating film. A pillar-shaped semiconductor layer is on the fin-shaped semiconductor layer, and a gate insulating film is around the pillar-shaped semiconductor layer. A gate electrode is around the gate insulating film and is made of a third metal. A gate line is connected to the gate electrode, and an upper portion of the fin-shaped semiconductor layer and the first metal film are electrically connected to each other.
    Type: Grant
    Filed: August 9, 2017
    Date of Patent: June 19, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9991381
    Abstract: A semiconductor-device production method includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer, and a second step of, after the first step, forming a second insulating film around the fin-shaped semiconductor layer, depositing a first polysilicon on the second insulating film to achieve planarization, forming, in a direction perpendicular to a direction of the fin-shaped semiconductor layer, a second resist for forming a first gate line and a first pillar-shaped semiconductor layer and a third resist for forming a first contact line and a second pillar-shaped semiconductor layer, and etching the first polysilicon, the second insulating film, and the fin-shaped semiconductor layer to form the first pillar-shaped semiconductor layer, a first dummy gate formed from the first polysilicon, the second pillar-shaped semiconductor layer, and a second dummy gate formed from the first polysilicon.
    Type: Grant
    Filed: July 13, 2015
    Date of Patent: June 5, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20180138294
    Abstract: A method for producing a semiconductor device includes depositing a first insulating film and a second insulating film on a planar semiconductor layer formed on a substrate; forming a first hole for forming a gate electrode in the second insulating film; filling the first hole with a first metal to form the gate electrode; forming a side wall formed of a third insulating film on an upper surface of the gate electrode and a side surface of the first hole; performing etching through, as a mask, the side wall formed of the third insulating film, to form a second hole in the gate electrode and the first insulating film; forming a gate insulating film on a side surface of the second hole; and epitaxially growing a semiconductor layer, within the second hole, on the planar semiconductor layer to form a first pillar-shaped semiconductor layer.
    Type: Application
    Filed: December 20, 2017
    Publication date: May 17, 2018
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA, Nozomu HARADA
  • Patent number: 9972722
    Abstract: A method for producing a semiconductor device includes a first step of forming a fin-shaped semiconductor layer on a semiconductor substrate and forming a first insulating film around the fin-shaped semiconductor layer; a second step of forming a pillar-shaped semiconductor layer and a first dummy gate formed of a first polysilicon; a third step of forming a second dummy gate on side walls of the first dummy gate and the pillar-shaped semiconductor layer; a fourth step of forming a side wall formed of a fifth insulating film around the second dummy gate, forming a second diffusion layer in an upper portion of the fin-shaped semiconductor layer and a lower portion of the pillar-shaped semiconductor layer, and forming a metal-semiconductor compound on the second diffusion layer; a fifth step of forming a gate electrode and a gate line; and a sixth step of depositing a sixth insulating film, forming a third resist for forming a contact hole on the pillar-shaped semiconductor layer, etching the sixth insulating f
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: May 15, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20180122940
    Abstract: A semiconductor device includes a planar semiconductor layer formed on a substrate; a pillar-shaped semiconductor layer formed on the planar semiconductor layer; a gate insulating film surrounding the pillar-shaped semiconductor layer; a first metal surrounding the gate insulating film, the first metal being in contact with an upper portion of the planar semiconductor layer; a gate formed above the first metal so as to surround the gate insulating film, the gate being electrically insulated from the first metal; and a second metal formed above the gate so as to surround the gate insulating film, the second metal being electrically insulated from the gate, the second metal having an upper portion electrically connected to an upper portion of the pillar-shaped semiconductor layer.
    Type: Application
    Filed: December 29, 2017
    Publication date: May 3, 2018
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 9960277
    Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer on a semiconductor substrate; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, etching back the second polysilicon, depositing a sixth insulating film, forming a fourth resist, forming a second hard mask, forming a third hard mask, forming a second dummy gate, and forming a first dummy contact on the fin-shaped semiconductor layer.
    Type: Grant
    Filed: November 28, 2017
    Date of Patent: May 1, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9954032
    Abstract: A method for producing a memory device and semiconductor device includes forming pillar-shaped phase change layers and lower electrodes in two or more rows and two or more columns on a semiconductor substrate. A reset gate insulating film is formed that surrounds the pillar-shaped phase change layers and the lower electrodes, and a reset gate is formed that surrounds the pillar-shaped phase change layers that function as memory devices arranged in two or more rows and two or more columns.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: April 24, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Patent number: 9947670
    Abstract: A static random access memory (SRAM) device includes an inverter including a ninth first-conductivity-type semiconductor layer formed on a semiconductor substrate; a first pillar-shaped semiconductor layer which is formed on the semiconductor substrate and in which a first first-conductivity-type semiconductor layer, a first body region, a second first-conductivity-type semiconductor layer, a first second-conductivity-type semiconductor layer, a second body region, and a second second-conductivity-type semiconductor layer are formed from the substrate side in that order; a first gate insulating film formed around the first body region; a first gate formed around the first gate insulating film; a second gate insulating film formed around the second body region; a second gate formed around the second gate insulating film; and a first output terminal connected to the second first-conductivity-type semiconductor layer and the first second-conductivity-type semiconductor layer.
    Type: Grant
    Filed: June 18, 2015
    Date of Patent: April 17, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20180089933
    Abstract: A game system of the present invention is configured to move a character image displayed in said display area of the single display, after the game on the game devices are interrupted, the character image being for indicating the game device to receive the prize, and stop the character image on the display of the game device to receive the prize, after a predetermined period from the beginning of moving the character image.
    Type: Application
    Filed: April 21, 2017
    Publication date: March 29, 2018
    Inventors: Kenji ENOKIDO, Hiroki NAKAMURA, Ken YOSHIKAWA, Yukihiro KAWAKAMI
  • Publication number: 20180089934
    Abstract: A display state in which the specific symbol is displayed in all the rows of any of N columns continuously from one side of a symbol matrix to another side, a prize of the rank corresponding to the columns with the specific symbols displayed on all the rows of the columns is awarded.
    Type: Application
    Filed: April 21, 2017
    Publication date: March 29, 2018
    Inventors: Kenji ENOKIDO, Hiroki NAKAMURA, Ken YOSHIKAWA, Yukihiro KAWAKAMI
  • Publication number: 20180090623
    Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer on a semiconductor substrate; a second step of forming a second insulating film, depositing a first polysilicon, planarizing the first polysilicon, forming a third insulating film, forming a second resist, and forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; and a third step of forming a fourth insulating film, depositing a second polysilicon, planarizing the second polysilicon, etching back the second polysilicon, depositing a sixth insulating film, forming a fourth resist, forming a second hard mask, forming a third hard mask, forming a second dummy gate, and forming a first dummy contact on the fin-shaped semiconductor layer.
    Type: Application
    Filed: November 28, 2017
    Publication date: March 29, 2018
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 9929341
    Abstract: A semiconductor device includes first pillar-shaped semiconductor layers, a first gate insulating film formed around the first pillar-shaped semiconductor layers, gate electrodes formed around the first gate insulating film, gate lines connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped semiconductor layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped semiconductor layers, diffusion layers formed in lower portions of the first pillar-shaped semiconductor layers, pillar-shaped insulator layers formed on the second contacts, variable-resistance films formed around upper portions of the pillar-shaped insulator layers, and lower electrodes formed around lower portions of the pillar-shaped insulator layers and connected to the variable-resistance f
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: March 27, 2018
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20180083138
    Abstract: A semiconductor device includes a fin-shaped semiconductor layer on a semiconductor substrate and a first insulating film around the fin-shaped semiconductor layer. A first contact is on the fin-shaped semiconductor layer, where the first contact is metal contact. A first gate insulating film is around the first contact and a fourth contact on the first contact, and a second gate insulating film is around the fourth contact.
    Type: Application
    Filed: November 1, 2017
    Publication date: March 22, 2018
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Publication number: 20180062009
    Abstract: A semiconductor device includes a pillar-shaped semiconductor layer formed on a planar semiconductor layer, a first insulator surrounding the pillar-shaped semiconductor layer, a first gate surrounding the first insulator and made of a metal having a first work function, a second gate surrounding the first insulator and made of a metal having a second work function different from the first work function, a third gate surrounding the first insulator and made of a metal having the first work function, a first metal layer surrounding the first insulator and having a third work function, and a second metal layer surrounding the first insulator and having the third work function. The first gate, the second gate, and the third gate are electrically connected together.
    Type: Application
    Filed: October 25, 2017
    Publication date: March 1, 2018
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 9905755
    Abstract: A semiconductor device includes first pillar-shaped silicon layers, a first gate insulating film formed around the first pillar-shaped silicon layers, gate electrodes formed of metal and formed around the first gate insulating film, gate lines formed of metal and connected to the gate electrodes, a second gate insulating film formed around upper portions of the first pillar-shaped silicon layers, first contacts formed of a first metal material and formed around the second gate insulating film, second contacts formed of a second metal material and connecting upper portions of the first contacts and upper portions of the first pillar-shaped silicon layers, diffusion layers formed in lower portions of the first pillar-shaped silicon layers, and variable-resistance memory elements formed on the second contacts.
    Type: Grant
    Filed: April 17, 2017
    Date of Patent: February 27, 2018
    Assignee: Unisantis Electronics Singapore Pte. Ltd.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20180047823
    Abstract: A semiconductor device includes a pillar-shaped semiconductor layer formed on a substrate; a first insulator surrounding the pillar-shaped semiconductor layer; a first gate surrounding the first insulator and made of a metal having a first work function; a second gate surrounding the first insulator and made of a metal having a second work function different from the first work function, the second gate being located below the first gate; a third gate surrounding the first insulator and made of a metal having the first work function, the third gate being located below the second gate; and a fourth gate surrounding the first insulator and made of a metal having the second work function different from the first work function, the fourth gate being located below the third gate. The first gate, the second gate, the third gate, and the fourth gate are electrically connected together.
    Type: Application
    Filed: October 19, 2017
    Publication date: February 15, 2018
    Inventors: Fujio MASUOKA, Hiroki NAKAMURA
  • Patent number: 9893179
    Abstract: A method for producing a semiconductor device includes a first step of forming a first insulating film around a fin-shaped semiconductor layer on a semiconductor substrate; a second step of forming a pillar-shaped semiconductor layer, a first dummy gate, and a first hard mask; a third step of forming a second hard mask, forming a second dummy gate, and forming a first dummy contact; a fourth step of forming a sidewall and forming a metal-semiconductor compound in an upper portion of a second diffusion layer; a fifth step of forming a gate electrode, a gate line, and a first contact; and a sixth step of forming a second contact, a third contact made of a second metal, and a fourth contact made of the second metal.
    Type: Grant
    Filed: June 24, 2016
    Date of Patent: February 13, 2018
    Assignee: UNISANTIS ELECTRONICS SINGAPORE PTE. LTD.
    Inventors: Fujio Masuoka, Hiroki Nakamura
  • Publication number: 20180038024
    Abstract: A holding material including: inorganic fibers that include 70 wt % or more of an alumina component an organic binder other than polyacrylamide of which the surface is negatively charged, alumina sol, and polyacrylamide having a weight-average molecular weight of 3,000,000 to 6,000,000, wherein the amount of the alumina sol is 2 to 8 parts by weight relative to 100 parts by weight of the amount of the inorganic fibers, and the amount of the polyacrylamide is 0.01 to 1.0 parts by weight relative to 100 parts by weight of the amount of the inorganic fibers.
    Type: Application
    Filed: February 25, 2016
    Publication date: February 8, 2018
    Applicant: NICHIAS CORPORATION
    Inventors: Akihiro NAKASHIMA, Kazutoshi ISOMURA, Hiroki NAKAMURA, Yuki TAKEDA