Patents by Inventor Hiroki Tanaka

Hiroki Tanaka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11971288
    Abstract: A level meter includes light emission segments forming an emission region, a register portion to register a default emission condition and an emission-condition specified value, and a control portion. The control portion controls the light emission so that the emission region spreads in an emission proceeding direction according to an increase in numerical quantity to be expressed. An emission-condition specified value indicates a command to apply a predetermined specified emission condition concerning a subsequent segment positioned on a more upstream side than a foremost segment positioned on a most downstream side in the emission proceeding direction. The control portion allows all the light emission segments forming the emission region to emit light based on the default emission condition, and the control portion allows the foremost segment to emit light based on the default emission condition whereas allowing the subsequent segment to emit light based on the specified emission condition.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: April 30, 2024
    Assignee: PATLITE CORPORATION
    Inventor: Hiroki Tanaka
  • Patent number: 11970390
    Abstract: The present disclosure provides a method for producing a microchannel device, which can form a channel that has high hydrophobicity, high solvent resistance as well, and also resistance to heat and damage, on demand with high accuracy, and produces the microchannel device at a low cost, while having high productivity. The method for producing a microchannel device includes: forming a channel pattern from a hydrophobic resin on a porous substrate by an electrophotographic method; melting the channel pattern by heat to allow the channel pattern to permeate into the porous substrate, thereby forming a channel in the inside of the porous substrate.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: April 30, 2024
    Assignee: Canon Kabushiki Kaisha
    Inventors: Takeshi Yamamoto, Jun Miura, Keiji Miyazaki, Hiroki Tanaka, Makoto Fukatsu, Akihisa Matsukawa, Takayuki Kanazawa, Keigo Mizusawa, Masanori Seki, Masanori Tanaka
  • Publication number: 20240132187
    Abstract: A ship monitoring system includes: a shipboard information processing apparatus and including a shipboard communication unit and an information acquisition unit; and a support information processing apparatus and including: a support side communication unit capable of communicating with the shipboard communication unit; a time lag identification unit; and a state prediction unit. The time lag identification unit identifies a time from transmission of the ship motion information from the shipboard communication unit to reception of the ship motion information by the support side communication unit as a reception time lag. The state prediction unit inputs the ship motion information and the reception time lag to a ship motion model related to the ship motion of the ship to predict a motion state of the ship ahead of a motion state of the ship indicated by the ship motion information by a period of time based on the reception time lag.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 25, 2024
    Inventors: Toru KAWATANI, Hiroki TANAKA, Takatsugu SAKAKIBARA, Naoyuki KAWASAKI, Ryo YAMAGUCHI, Hironobu UETAKE, Naoki SHIMADA, Kenta ABE
  • Publication number: 20240134377
    Abstract: In a ship control system of one embodiment, a main engine controller performs, when controlling the rotational frequency of a main engine based on a target ship speed of a ship, feedback control of an actual ship speed of the ship to perform ship speed control for bringing the actual ship speed closer to the target ship speed. A turning judgment unit judges whether or not the ship will turn. A control change unit performs, when the turning judgment unit has judged that the ship will turn, lowering processing for lowering the responsiveness of the ship speed control.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 25, 2024
    Inventors: Toru KAWATANI, Hiroki TANAKA, Takatsugu SAKAKIBARA, Naoyuki KAWASAKI, Ryo YAMAGUCHI, Hironobu UETAKE, Naoki SHIMADA, Kenta ABE
  • Publication number: 20240134077
    Abstract: A fiber sensing system according to the present disclosure includes a submarine cable, and a plurality of relaying apparatuses being connected in series to one another via the submarine cable. The relaying apparatus includes a DAS interrogator being connected to a relaying apparatus at a subsequent stage via a sensing optical fiber in the submarine cable, and a terminator being connected to a relaying apparatus at a preceding stage via the sensing optical fiber. The DAS interrogator outputs probe light to the sensing optical fiber. The terminator terminates probe light being output from the DAS interrogator in the relaying apparatus at the preceding stage to the sensing optical fiber. The DAS interrogator receives backscattered light of probe light from the sensing optical fiber, and acquires the DAS data from the received backscattered light.
    Type: Application
    Filed: October 10, 2023
    Publication date: April 25, 2024
    Applicant: NEC Corporation
    Inventors: Masafumi EMURA, Yuta Sawai, Hiroki Tanaka, Minoru Kobayashi
  • Publication number: 20240132186
    Abstract: In a ship control system of one embodiment, a route command unit outputs a route command including a target ship position and a target bow direction of a ship. An information detector detects ship information including an actual ship position and an actual bow direction of a ship. An external force vector estimation unit estimates an external force vector received by a ship, using the ship information and a hull motion model related to a hull motion of the ship. A control command unit controls both rotational frequency of a main engine and a rudder angle of a ship, based on the route command, the ship information, and the external force vector.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 25, 2024
    Inventors: Toru KAWATANI, Hiroki TANAKA, Takatsugu SAKAKIBARA, Naoyuki KAWASAKI, Ryo YAMAGUCHI, Hironobu UETAKE, Naoki SHIMADA, Kenta ABE
  • Patent number: 11964479
    Abstract: A medium feeding device includes a feeding roller that is provided in a medium feeding path through which a medium is fed and that feeds a medium downstream by rotating in the forward direction in response to power of a motor, a nip roller that is provided in the medium feeding path and that nips a medium in cooperation with the feeding roller and rotates, and a controller configured to control the motor. Based on an increase in a variation value varying in accordance with a drive load of the motor, the controller controls the motor and causes the feeding roller to start a medium feeding operation.
    Type: Grant
    Filed: December 21, 2020
    Date of Patent: April 23, 2024
    Assignee: Seiko Epson Corporation
    Inventors: Keisuke Sasaki, Takayuki Tanaka, Hiroki Shinagawa
  • Publication number: 20240128247
    Abstract: Embodiments described herein enable a microelectronic assembly that includes: a first substrate comprising glass and at least one inductor, the first substrate having a first side and an opposing second side; a second substrate coupled to the first side of the first substrate; and a plurality of integrated circuit (IC) dies. A first subset of the plurality of IC dies is directly coupled to the second side of the first substrate, a second subset of the plurality of IC dies is directly coupled to the second substrate adjacent to the first substrate, and a third subset of the plurality of IC dies is embedded in the second substrate between the first substrate and the second subset of the plurality of IC dies.
    Type: Application
    Filed: October 14, 2022
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Brandon C. Marin, Kristof Kuwawi Darmawikarta, Srinivas V. Pietambaram, Gang Duan, Jeremy Ecton, Suddhasattwa Nad, Hiroki Tanaka
  • Publication number: 20240128181
    Abstract: Embodiments of a microelectronic assembly that includes: a package substrate comprising a plurality of layers of organic dielectric material and conductive traces alternating with conductive vias in alternate layers of the organic dielectric material; and a plurality of integrated circuit dies coupled to a first side of the package substrate by interconnects, in which: the plurality of layers of the organic dielectric material comprises at least a first layer having a conductive via and a second layer having a conductive trace in contact with the conductive via, the second layer is not coplanar with the first layer, sidewalls of the conductive via are orthogonal to the conductive trace, and two opposing sidewalls of the conductive via separated by a width of the conductive via protrude from respectively proximate edges of the conductive trace by a protrusion that is at least ten times less than the width of the conductive via.
    Type: Application
    Filed: October 17, 2022
    Publication date: April 18, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Brandon C. Marin, Srinivas V. Pietambaram, Hiroki Tanaka, Haobo Chen
  • Patent number: 11960224
    Abstract: A fixing device includes an endless belt, a rotatable pressing member, a pad member inside of the belt, and a sliding member held by the pad member and sliding on an inner circumferential surface of the belt in a nip. The rotatable pressing member nips and feeds a recording material in the nip in cooperation with the belt and fixes a toner image on the recording material by applying heat and pressure. The sliding member includes a base material layer on which a plurality of projections projecting toward the rotatable pressing member are formed on a side sliding with the belt and a sliding layer provided on an outer surface of the plurality of projections. A leading end of the plurality of projections is a plane and an average roughness (Ra) of the plane satisfies 0.13 ?m?Ra?1.67 ?m.
    Type: Grant
    Filed: February 16, 2023
    Date of Patent: April 16, 2024
    Assignee: CANON KABUSHIKI KAISHA
    Inventors: Akiyoshi Shinagawa, Yasuharu Toratani, Hiroshi Miyamoto, Daigo Matsuura, Hiroki Kawai, Ayano Ogata, Masanobu Tanaka, Asuna Fukamachi, Misa Kawashima
  • Patent number: 11962654
    Abstract: A communication system according to an embodiment includes a server system and one or more communication apparatuses. The server system includes a first hardware processor. The first hardware processor determines frequency information indicating processing frequency of predetermined processing executed by the communication apparatuses. The frequency information is determined on the basis of determination information affecting the predetermined processing. The first hardware processor transmits processing frequency of the predetermined processing to the communication apparatuses. The processing frequency is determined on the basis of the frequency information. The communication apparatuses each include a second hardware processor. The second hardware processor receives the processing frequency of the processing from the server system. The second hardware processor executes the predetermined processing on the basis of the received processing frequency.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: April 16, 2024
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yasuyuki Tanaka, Suh Wuk Kim, Hiroki Kudo, Sakie Nagakubo
  • Publication number: 20240111090
    Abstract: A device comprises a substrate and an IC die, which may be a photonic IC. The substrate comprises a first surface, a second surface opposite the first surface, an optical waveguide integral with the substrate, and a hole extending from the first surface to the second surface. The hole comprises a first sidewall. The optical waveguide is between the first surface and the second surface, parallel to the first surface, and comprises a first end which extends to the first sidewall. The IC die is within the hole and comprises a second sidewall and an optical port at the second sidewall. The second sidewall is proximate to the first sidewall and the first end of the optical waveguide is proximate to and aligned with the optical port. The substrate may include a recess to receive another device comprising a socket.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Robert A. May, Tarek Ibrahim, Shriya Seshadri, Kristof Darmawikarta, Hiroki Tanaka, Changhua Liu, Bai Nie, Lilia May, Srinivas Pietambaram, Zhichao Zhang, Duye Ye, Yosuke Kanaoka, Robin McRee
  • Publication number: 20240112972
    Abstract: Disclosed herein are microelectronics package architectures utilizing photo-integrated glass interposers and photonic integrated glass layers and methods of manufacturing the same. The microelectronics packages may include an organic substrate, a photonic integrated glass layer, and a glass interpose. The organic substrate may define through substrate vias. The photonic integrated glass layer may be attached to the organic substrate. The photonic integrated glass layer may include photo detectors. The glass interposer may be attached to the organic substrate. The glass interposer may define through glass vias in optical communication with the photo detectors.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Hiroki Tanaka, Robert Alan May, Kristof Darmawikarta, Bai Nie, Brandon C. Marin, Jeremy D. Ecton, Srinivas Venkata Ramanuja Pietambaram, Changhua Liu
  • Publication number: 20240113029
    Abstract: Multi-die packages including at least one glass substrate within a space between two adjacent IC dies or surrounding an interconnect bridge die. The various IC dies may be placed within recesses formed in the glass substrate. The IC die and glass substrate, along with any conductive vias extending through the glass substrate may be planarized. The bridge die may be directly bonded or soldered to the adjacent IC dies, providing fine pitch interconnect. The opposite side of the adjacent IC dies and glass substrate may be attached to a host component or may be built up with package dielectric material. Metallization features formed on the second side of the glass substrate may electrically interconnect the IC dies to package interconnect interfaces that may be further coupled to a host with solder interconnects.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Brandon Marin, Srinivas Pietambaram, Hiroki Tanaka, Suddhasattwa Nad
  • Publication number: 20240113005
    Abstract: Microelectronic integrated circuit package structures include a first substrate coupled to a second substrate by a conductive interconnect structure and a dielectric material adjacent to the conductive interconnect structure. A cavity in a surface of the first substrate is adjacent to the conductive interconnect structure. A portion of the dielectric material is within the cavity.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Applicant: Intel Corporation
    Inventors: Jeremy Ecton, Aleksandar Aleksov, Hiroki Tanaka, Brandon Marin, Srinivas Pietambaram, Xavier Brun
  • Publication number: 20240111095
    Abstract: A hybrid plasmonic waveguide and associated methods are disclosed. In one example, the electronic device includes combining an electromagnetic wave propagating in a waveguide with a high refractive index and a surface plasmon from a metal surface to create a hybrid plasmon wave in a low refractive index material separating the dielectric waveguide and metal surface. In selected examples, surface mounted hybrid plasmonic waveguides are shown. In selected examples hybrid plasmonic waveguides embedded in glass interposers are shown.
    Type: Application
    Filed: September 30, 2022
    Publication date: April 4, 2024
    Inventors: Hiroki Tanaka, Brandon C. Marin, Robert Alan May, Suddhasattwa Nad, Benjamin Duong
  • Patent number: 11948848
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a substrate and a conductive feature over the substrate. In an embodiment, a metallic mask is positioned over the conductive feature. In an embodiment, the metallic mask extends beyond a first edge of the conductive feature and a second edge of the conductive feature.
    Type: Grant
    Filed: February 12, 2019
    Date of Patent: April 2, 2024
    Assignee: Intel Corporation
    Inventors: Jeremy Ecton, Oscar Ojeda, Leonel Arana, Suddhasattwa Nad, Robert May, Hiroki Tanaka, Brandon C. Marin
  • Publication number: 20240105576
    Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core and a pad over the core. In an embodiment, a solder resist is over the pad, and an opening into the solder resist exposes a portion of the pad. In an embodiment, the package substrate further comprises a surface finish over the pad and within the opening.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventors: Kyle MCELHINNY, Xiaoying GUO, Hiroki TANAKA, Haobo CHEN
  • Publication number: 20240105580
    Abstract: Embodiments disclosed herein include electronic packages and methods of forming such packages. In an embodiment, the electronic package comprises a core, and a pad over the core. In an embodiment, a shell is around the core, and a surface finish is over the shell. In an embodiment, the electronic package further comprises a solder resist over the pad, where an opening is formed through the solder resist to expose the surface finish.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventors: Kristof DARMAWIKARTA, Srinivas V. PIETAMBARAM, Kyle MCELHINNY, Hiroki TANAKA
  • Publication number: 20240105575
    Abstract: Embodiments disclosed herein include package substrates and methods of forming package substrates. In an embodiment, the package substrate comprises a core, and a pad over the core, where the pad has a first width. In an embodiment, a surface finish is over the pad, where the surface finish has a second width that is substantially equal to the first width. In an embodiment, the package substrate further comprises a solder resist over the pad, where the solder resist comprises an opening that exposes a portion of the surface finish. In an embodiment, the opening has a third width that is smaller than the second width.
    Type: Application
    Filed: September 26, 2022
    Publication date: March 28, 2024
    Inventors: Jason M. GAMBA, Haifa HARIRI, Kristof DARMAWIKARTA, Srinivas V. PIETAMBARAM, Hiroki TANAKA, Kyle MCELHINNY, Xiaoying GUO, Steve S. CHO, Ali LEHAF, Haobo CHEN, Bai NIE, Numair AHMED