Abstract: A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.

Abstract: A small, lightweight and inexpensive thin-form centrifugal fan having a first moving blade; a second moving blade; and a stationary blade disposed between the first moving blade and the second moving blade and directing gas taken in by rotation of the first moving blade to the second moving blade. The first and second moving blades are formed such that the rigidity of their central portions is smaller than the rigidity of their outer perimeter areas.

Abstract: A server device having a content provider, a voice provider and an access number counter, etc. is arranged on the Internet. The content provider provides terminal devices connected to the Internet with the contents (e.g., contents of a chat) which are updated at predetermined intervals. The access number counter counts the number of terminal devices which have currently logged in to the contents provided by the content provider and have not logged out therefrom. The voice provider sets a voice level in accordance with a value counted by the access number counter, every time new contents are provided by the content provider, and provides voice data.

Abstract: The power supply-voltage dependency of a current source current is reduced and the power supply voltage is lowered. The invention includes an emitter-coupled logic circuit 118 and a reference-voltage generating circuit 119 for generating a reference voltage VCSC for controlling a drain current (=current source current ICS) of a constant current-supplying n-type MOS transistor 110. The emitter-coupled logic circuit 118 comprises a current switch made up of a pair of emitter-coupled bipolar transistors 106 and 107, a constant current-supplying n-type MOS transistor 110 that is connected in series with the current switch, and resistor means 108 and 109 connected in series with the bipolar transistors 106 and 107 individually for obtaining an output voltage.

Abstract: A semiconductor memory has a memory cell matrix encompassing (a) device isolation films running along the column-direction, arranged alternately between the memory cell transistors aligned along the row-direction, (b) first conductive layers arranged along the row and column-directions, top surfaces of the first conductive layers lie at a lower level than top surfaces of the device isolation films, (c) an inter-electrode dielectric arranged both on the device isolation films and the first conductive layers so that the inter-electrode dielectric can be shared by the memory cell transistors belonging to different cell columns' relative dielectric constant of the inter-electrode dielectric is higher than relative dielectric constant of the device isolation films, and (d) a second conductive layer running along the row-direction, arranged on the inter-electrode dielectric. Here, upper corners of the device isolation films are chamfered.

Abstract: A semiconductor memory encompasses a memory cell matrix, which embraces device isolation films running along the column-direction, arranged alternatively between the cell columns; first conductive layers having top surfaces lower than the device isolation films; inter-electrode dielectrics arranged on the corresponding first conductive layers, the inter-electrode dielectric has a dielectric constant larger than that of silicon oxide; and second conductive layers running along the row-direction, each of the second conductive layers arranged on the inter-electrode dielectric and the device isolation films so that the second conductive layer can be shared by the memory cell transistors arranged along the row-direction belonging to different cell columns.

Abstract: A signal transmit-receive device that reduces the number of high-speed signal lines required for connecting a transmitting circuit group and a receiving circuit group and for running a loopback test on a signal transmit-receive device for signal communication, and reduces installation costs and power consumption. The new loopback test circuit uses an error detecting circuit within the transmitting circuit IC, a test signal producing circuit within the receiving circuit IC, and a wiring for transmitting error information from the transmitting circuit to the receiving circuit. The error detecting circuit compares a test signal pattern defined in advance by a first communication device and a received signal pattern to detect errors. The test signal producing circuit produces a test signal pattern defined in advance by the first communication device, and can invert any bits of the test signal pattern, based on error information.

Abstract: The present invention is directed to an image processing apparatus. The apparatus comprises alteration means for altering the content of a first image file, read from a recording medium, in accordance with a user's instruction, and generating a second image file; and control means for, if authentication data is added to said first image file, recording said second image file onto said recording medium without deleting said first image file.

Abstract: An on-chip multiprocessor having a chip layout for efficient multiprocessor control, wherein multiple processors and shared portions such as shared caches are symmetric with respect to a desired linear axis and a multiprocessor controller is located in the area containing said linear axis. This makes the distances between the processors and the controller equal and shorter, and also decreases differences in the distance between the controller and shared portions, thereby permitting higher speed processing of signals among these.

Abstract: A server device and a client device are connected through the Internet and the server device provides predetermined information on demand by the client device. The client device starts obtaining time when it displays predetermined information provided by the server device and stops obtaining time when a response to displayed predetermined information is input. That is, the client device obtains the time period between a display of predetermined information and an input of the response. The client device sends the obtained time period to the server device through the Internet. The server device certifies the received time period. At the time of certifying, the server device checks if the time period data and the program for obtaining the time period are improperly altered or not.

Abstract: The present invention relates to a PLL circuit and a voltage controlled oscillator wherein a clock signal jitter caused when the supply voltage fluctuates of which is small can be supplied, and the voltage controlled oscillator is provided with a MOS transistor to one end of which a first power source (Vss) is connected and to the gate electrode of which a control signal for controlling the oscillation frequency is input, an oscillator connected between the other end of the MOS transistor and a second power source (Vdd) and a capacitative element connected to the oscillator in parallel and is further provided with additive control means for minutely controlling the oscillation frequency.

Abstract: A clock data recovery circuit has a good jitter tolerance characteristic and a broad data recovery range in the event of a wander, that is, a good wander-tracking characteristic of a recovered clock signal. The clock data recovery circuit executes control to compare the position of the edge of data with the position of the edge of a data recovery clock signal (a recovered clock signal) and keeps the clock edge away from the data edge if a gap between the edges becomes smaller than a reference value. A cycle of a reference clock signal is divided into N portions to generate N clock signals (pl) with phases different from each other in composition circuits. By executing control to turn on 2 of the N selector control signals supplied to each 2 adjacent pins of the N−1 selectors at the same time, the N−1 selectors are capable of generating a middle phase between first and second phases and, hence, generating one of N×2 phases from N input phases as the phase of the data recovery clock signal.

Abstract: A small, lightweight and inexpensive thin-form centrifugal fan having a first moving blade; a second moving blade; and a stationary blade disposed between the first moving blade and the second moving blade and directing gas taken in by rotation of the first moving blade to the second moving blade. The first and second moving blades are formed such that the rigidity of their central portions is smaller than the rigidity of their outer perimeter areas.

Abstract: The communication apparatus is equipped with a first communication interface for executing communication based on a first communication method, and a second communication interface for executing communication based on a second communication method different from the first communication method. The communication apparatus sets ID information for identifying device executing communication by the first communication method, for device which executes communication with the second communication interface. In this manner plural device supporting different communication methods can be recognized as device belonging to a same communication system.

Abstract: A logic circuit determines the power consumption of a semiconductor integrated device by taking into consideration the variation of the rate of operation. A control signal (TEST) is applied to each control signal input port (Tin) of flip-flop circuits of flip-flop circuit groups and a logic gate circuit having a plurality of input ports A and B in a combined circuit group. If the control signal (TEST) is low, both the flip-flop circuits and the logic gate circuit operate normally. However, if the control signal (TEST) is high, each of them performs the power consumption test. Regardless of the value of input signals applied to input ports D1 and D2 of the flip-flop circuits, the flip-flop circuits are controlled to have a repetitive output signal of high and low levels at ports Q1 and Q2, in synchronism with a clock signal.

Abstract: An agent device is connected to a user device for browsing a merchant site, for selling products online and being served up on the Internet, the merchant site, and a server device of a credit-card company. In the case where an instruction of purchasing a product browsed by the user device is output, the instruction is sent to the agent device. The agent device extracts a credit card number of a credit card held by a user having purchased the product, and inquires of the server device of the credit card company whether the product is to be purchased with the credit card. As an inquiry result, in the case where the product can be purchased online with the credit card, the agent device sends an instruction that the user purchases the product online with the credit card.

Abstract: When persons who meet each other in the business scene exchange their business cards, and business card IDs specific to themselves and send the obtained other person's business card ID together with information indicating the situation when the IDs are exchanged, from the cellular phones to register the ID in the business card managing server. The business card managing server includes user's own information databases, besides other persons' information databases. A user who intends to browse another person's business card information, sends the user's own business card ID and the other person's business card ID to the business card managing server from the business card managing client. The business card managing server retrieves necessary information from the other persons' information database of the user and the user's own information database of the other person, and sends retrieved information to the business card managing client as the business card information.

Abstract: The delay time for the transfer of data signals between pluralities of logic circuits is automatically regulated to be in a desired range. In order to regulate the delay time of the data signal transfer, a common standard signal SYNC is distributed to the logic circuits from a standard signal generator source. In the sending side of one logic circuit, the standard signal is applied through a selector circuit to a flip-flop circuit and then transferred to the receiving side of another logic circuit. Specifically, the transferred standard signal passes through a variable delay circuit to a flip flop circuit on the receiving side of the other logic circuit where it is compared with the standard signal received from the standard signal generator source, which has passed through a delay circuit of a standard delay value. The result of the comparison is used to adjust the variable delay circuit that controls the delay time for the transferred standard signal.

Abstract: A belt drive used in image forming apparatuses which minimizes the transverse movement of the belt across the length of a roller and prevents the riding up of the belt onto the roller. The belt drive device has a belt equipped with elastic guide members mounted on each edge or on the back surface of the belt near each edge. The belt is suspended over two or more rollers and driven by the drive belt. At least one of the rollers is a drive roller having a rotating member mounted between the elastic guide member and the roller end area such that the rotating members rotate independently of the roller.

Abstract: A condenser having a huge area is required to reduce a noise on LSI power supply nets (−&Dgr;VDD) of an integrated circuit because a bypass condenser can only utilize a part of accumulated electric charges. A noise of LSI power supply nets is suppressed by generating a noise of a reversed polarity (+&Dgr;VDD) to the noise on the LSI power supply nets (−&Dgr;VDD), based upon a noise reducing circuit discharging a condenser charged with a high voltage. A noise reduction effect equivalent to a bypass condenser having a large capacity is obtained even when a condenser having a small capacity is used.