Patents by Inventor Hiroko Koike

Hiroko Koike has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10857560
    Abstract: A rotary atomization type painting device includes an atomization head that supplies paint from a paint supply machine. The atomization head has an outer member that includes a truncated conical body, and an inner member that is disposed inside the outer member. The inner member has an annular protruding part that protrudes toward a large diameter side opening. The paint is lead out from a plurality of lead-out holes of the inner member to a root of the annular protruding part. At a root position in an axial direction, an angle in a lead-out direction of each of the lead-out holes with respect to an axis, and an angle of an inner surface of the annular protruding part with respect to the axis are made equal.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: December 8, 2020
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Naoki Kishimoto, Masaaki Shoji, Hiroko Koike, Koji Ikeda, Osamu Yashima
  • Publication number: 20190083997
    Abstract: A rotary atomization type painting device includes an atomization head that supplies paint from a paint supply machine. The atomization head has an outer member that includes a truncated conical body, and an inner member that is disposed inside the outer member. The inner member has an annular protruding part that protrudes toward a large diameter side opening. The paint is lead out from a plurality of lead-out holes of the inner member to a root of the annular protruding part. At a root position in an axial direction, an angle in a lead-out direction of each of the lead-out holes with respect to an axis, and an angle of an inner surface of the annular protruding part with respect to the axis are made equal.
    Type: Application
    Filed: July 20, 2016
    Publication date: March 21, 2019
    Inventors: Naoki Kishimoto, Masaaki Shoji, Hiroko Koike, Koji Ikeda, Osamu Yashima
  • Patent number: 7176052
    Abstract: A method of formation of a capacitor forming part of an electric circuit when producing a circuit board, consisting of forming a valve metal bottom electrode layer and a valve metal oxide dielectric layer on the same, then integrally forming a solid electrolyte layer comprised of an organic semiconductor and a top electrode layer comprised of metal on the same, this integral formation step consisting of the step of holding one surface of metal foil for the top electrode at a bonding wedge and making the other surface of the metal foil carry a powder of the organic semiconductor by compression bonding and heating and the step of compression bonding the organic semiconductor powder carried by compression bonding at the dielectric layer by a bonding wedge through metal foil, whereby a solid electrolyte layer comprised of an organic semiconductor sandwiched between the metal foil and dielectric layer and closely bonded with the two is formed, a capacitor built into a circuit board, a circuit board including a cap
    Type: Grant
    Filed: March 2, 2005
    Date of Patent: February 13, 2007
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hiroko Koike, Takashi Mochizuki, Mitsutoshi Higashi
  • Patent number: 7078311
    Abstract: There is provided a capacitor embedded in a substrate having a small thickness and requiring only a small space for short connection lines. The substrate-embedded capacitor comprises a substrate having an opening, a first conductive layer on the substrate, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and an insulating layer formed on the second conductive layer and having an opening. In the substrate-embedded capacitor, the first conductive layer and the second conductive layer are exposed through the openings in the substrate and the insulating layer, respectively.
    Type: Grant
    Filed: December 22, 2003
    Date of Patent: July 18, 2006
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Hideaki Sakaguchi, Hiroko Koike
  • Patent number: 7019405
    Abstract: In a terminal, a semiconductor device, a terminal forming method and a flip chip semiconductor device manufacturing method, it is possible to lessen damage to a semiconductor element due to vibration caused by an ultrasonic wave and settle misalignment and height unevenness of terminals. The terminal includes a pad provided on an active surface of an electric element having an IC chip, a metal post connected to the pad, and a projection electrode provided on the metal post.
    Type: Grant
    Filed: May 6, 2003
    Date of Patent: March 28, 2006
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hiroko Koike, Mitsutoshi Higashi, Hideaki Sakaguchi
  • Publication number: 20050144767
    Abstract: A method of formation of a capacitor forming part of an electric circuit when producing a circuit board, consisting of forming a valve metal bottom electrode layer and a valve metal oxide dielectric layer on the same, then integrally forming a solid electrolyte layer comprised of an organic semiconductor and a top electrode layer comprised of metal on the same, this integral formation step consisting of the step of holding one surface of metal foil for the top electrode at a bonding wedge and making the other surface of the metal foil carry a powder of the organic semiconductor by compression bonding and heating and the step of compression bonding the organic semiconductor powder carried by compression bonding at the dielectric layer by a bonding wedge through metal foil, whereby a solid electrolyte layer comprised of an organic semiconductor sandwiched between the metal foil and dielectric layer and closely bonded with the two is formed, a capacitor built into a circuit board, a circuit board including a cap
    Type: Application
    Filed: March 2, 2005
    Publication date: July 7, 2005
    Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.
    Inventors: Hiroko Koike, Takashi Mochizuki, Mitsutoshi Higashi
  • Patent number: 6903917
    Abstract: A capacitor is embedded in a substrate having a small thickness where only a small space for short connection lines is required. The substrate-embedded capacitor includes a substrate having an opening, a first conductive layer on the substrate, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and an insulating layer formed on the second conductive layer and having an opening. In the substrate-embedded capacitor, the first conductive layer and the second conductive layer are exposed through the openings in the substrate and the insulating layer, respectively.
    Type: Grant
    Filed: June 3, 2003
    Date of Patent: June 7, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Hideaki Sakaguchi, Hiroko Koike
  • Patent number: 6890792
    Abstract: A method of formation of a capacitor forming part of an electric circuit when producing a circuit board, consisting of forming a valve metal bottom electrode layer and a valve metal oxide dielectric layer on the same, then integrally forming a solid electrolyte layer comprised of an organic semiconductor and a top electrode layer comprised of metal on the same, this integral formation step consisting of the step of holding one surface of metal foil for the top electrode at a bonding wedge and making the other surface of the metal foil carry a powder of the organic semiconductor by compression bonding and heating and the step of compression bonding the organic semiconductor powder carried by compression bonding at the dielectric layer by a bonding wedge through metal foil, whereby a solid electrolyte layer comprised of an organic semiconductor sandwiched between the metal foil and dielectric layer and closely bonded with the two is formed, a capacitor built into a circuit board, a circuit board including a cap
    Type: Grant
    Filed: August 22, 2003
    Date of Patent: May 10, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Hiroko Koike, Takashi Mochizuki, Mitsutoshi Higashi
  • Patent number: 6864120
    Abstract: A semiconductor device comprises a substantially flat interconnection substrate having an interconnection pattern formed on a surface thereof. A semiconductor element is mounted on the substantially flat interconnection substrate so that an electrode terminal of the semiconductor element is electrically connected to the interconnection pattern. A heat radiation plate is formed in a form of a sheet having a concave portion so as to cover the semiconductor element and is bonded on the surface of the substantially flat interconnection substrate. An external connection terminal is formed on the other surface of the substantially flat interconnection substrate so as to penetrate through the substantially flat interconnection substrate and be electrically connected to the interconnection pattern. The heat radiation plate is formed of a heat-resistant resin containing carbon fibers.
    Type: Grant
    Filed: February 12, 2004
    Date of Patent: March 8, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi, Hiroko Koike
  • Patent number: 6861284
    Abstract: In a semiconductor device including an insulating core substrate, a plurality of layers of wiring patterns on the core substrate and insulating layers interposed between the wiring patterns, each adjacent pair of the wiring patterns being electrically connected through a conductor portion penetrating through the insulating layer interposed between them, each of the insulating layers is formed integrally, semiconductor chips thinner than one layer of the insulating layer are mounted into at least one of the insulating layers, and the semiconductor chips are electrically connected to one layer of the wiring pattern of one insulating layer adjacent on the side of the core substrate.
    Type: Grant
    Filed: January 2, 2003
    Date of Patent: March 1, 2005
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Kei Murayama, Hideaki Sakaguchi, Hiroko Koike
  • Publication number: 20040262735
    Abstract: In a semiconductor device including an insulating core substrate, a plurality of layers of wiring patterns on the core substrate and insulating layers interposed between the wiring patterns, each adjacent pair of the wiring patterns being electrically connected through a conductor portion penetrating through the insulating layer interposed between them, each of the insulating layers is formed integrally, semiconductor chips thinner than one layer of the insulating layer are mounted into at least one of the insulating layers, and the semiconductor chips are electrically connected to one layer of the wiring pattern of one insulating layer adjacent on the side of the core substrate.
    Type: Application
    Filed: May 24, 2004
    Publication date: December 30, 2004
    Inventors: Mitsutoshi Higashi, Kei Murayama, Hideaki Sakaguchi, Hiroko Koike
  • Publication number: 20040171214
    Abstract: A method of formation of a capacitor forming part of an electric circuit when producing a circuit board, consisting of forming a valve metal bottom electrode layer and a valve metal oxide dielectric layer on the same, then integrally forming a solid electrolyte layer comprised of an organic semiconductor and a top electrode layer comprised of metal on the same, this integral formation step consisting of the step of holding one surface of metal foil for the top electrode at a bonding wedge and making the other surface of the metal foil carry a powder of the organic semiconductor by compression bonding and heating and the step of compression bonding the organic semiconductor powder carried by compression bonding at the dielectric layer by a bonding wedge through metal foil, whereby a solid electrolyte layer comprised of an organic semiconductor sandwiched between the metal foil and dielectric layer and closely bonded with the two is formed, a capacitor built into a circuit board, a circuit board including a cap
    Type: Application
    Filed: August 22, 2003
    Publication date: September 2, 2004
    Applicant: Shinko Electric Industries Co., Ltd.
    Inventors: Hiroko Koike, Takashi Mochizuki, Mitsutoshi Higashi
  • Publication number: 20040166609
    Abstract: A semiconductor device comprises a substantially flat interconnection substrate having an interconnection pattern formed on a surface thereof. A semiconductor element is mounted on the substantially flat interconnection substrate so that an electrode terminal of the semiconductor element is electrically connected to the interconnection pattern. A heat radiation plate is formed in a form of a sheet having a concave portion so as to cover the semiconductor element and is bonded on the surface of the substantially flat interconnection substrate. An external connection terminal is formed on the other surface of the substantially flat interconnection substrate so as to penetrate through the substantially flat interconnection substrate and be electrically connected to the interconnection pattern. The heat radiation plate is formed of a heat-resistant resin containing carbon fibers.
    Type: Application
    Filed: February 12, 2004
    Publication date: August 26, 2004
    Inventors: Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi, Hiroko Koike
  • Publication number: 20040137695
    Abstract: There is provided a capacitor embedded in a substrate having a small thickness and requiring only a small space for short connection lines. The substrate-embedded capacitor comprises a substrate having an opening, a first conductive layer on the substrate, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and an insulating layer formed on the second conductive layer and having an opening. In the substrate-embedded capacitor, the first conductive layer and the second conductive layer are exposed through the openings in the substrate and the insulating layer, respectively.
    Type: Application
    Filed: December 22, 2003
    Publication date: July 15, 2004
    Inventors: Mitsutoshi Higashi, Hideaki Sakaguchi, Hiroko Koike
  • Patent number: 6713863
    Abstract: A semiconductor device comprises a substantially flat interconnection substrate having an interconnection pattern formed on a surface thereof. A semiconductor element is mounted on the substantially flat interconnection substrate so that an electrode terminal of the semiconductor element is electrically connected to the interconnection pattern. A heat radiation plate is formed in a form of a sheet having a concave portion so as to cover the semiconductor element and is bonded on the surface of the substantially flat interconnection substrate. An external connection terminal is formed on the other surface of the substantially flat interconnection substrate so as to penetrate through the substantially flat interconnection substrate and be electrically connected to the interconnection pattern. The heat radiation plate is formed of a heat-resistant resin containing carbon fibers.
    Type: Grant
    Filed: January 12, 2001
    Date of Patent: March 30, 2004
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi, Hiroko Koike
  • Publication number: 20030222326
    Abstract: In a terminal, a semiconductor device, a terminal forming method and a flip chip semiconductor device manufacturing method, it is possible to lessen damage to a semiconductor element due to vibration caused by an ultrasonic wave and settle misalignment and height unevenness of terminals. The terminal includes a pad provided on an active surface of an electric element having an IC chip, a metal post connected to the pad, and a projection electrode provided on the metal post.
    Type: Application
    Filed: May 6, 2003
    Publication date: December 4, 2003
    Inventors: Hiroko Koike, Mitsutoshi Higashi, Hideaki Sakaguchi
  • Publication number: 20030223177
    Abstract: There is provided a capacitor embedded in a substrate having a small thickness and requiring only a small space for short connection lines. The substrate-embedded capacitor comprises a substrate having an opening, a first conductive layer on the substrate, a dielectric layer on the first conductive layer, a second conductive layer on the dielectric layer, and an insulating layer formed on the second conductive layer and having an opening. In the substrate-embedded capacitor, the first conductive layer and the second conductive layer are exposed through the openings in the substrate and the insulating layer, respectively.
    Type: Application
    Filed: June 3, 2003
    Publication date: December 4, 2003
    Inventors: Mitsutoshi Higashi, Hideaki Sakaguchi, Hiroko Koike
  • Patent number: 6586845
    Abstract: A semiconductor device module includes one or a plurality of semiconductor devices, each including a semiconductor element having first and second surfaces, pads formed on the first surface on which electrode terminals are also formed and curved, flexible wires having first ends fixed to the pads. The semiconductor devices are mounted on a mounting board such that second ends of the wires are connected to terminals on the mounting board. A heat spreader has a recessed inner wall and a peripheral edge which is adhered to or engaged with the mounting board in such a manner that the second surfaces of the semiconductor elements face a bottom interior surface of the recessed inner wall. A thermal conductive resin layer of a substantially constant thickness is disposed between the second surface of the semiconductor element and the bottom interior surface of the recessed inner wall of the heat spreader.
    Type: Grant
    Filed: October 25, 1999
    Date of Patent: July 1, 2003
    Assignee: Shinko Electric Industries Co., Ltd.
    Inventors: Mitsutoshi Higashi, Hiroko Koike
  • Publication number: 20030102117
    Abstract: A heat radiation fin comprises a substrate having a high thermal conductivity and a plurality of heat radiation plates. The heat radiation plates are arranged upright on the substrate with predetermined intervals therebetween. Each of the heat radiation plates is formed of a heat-resistant resin containing carbon fibers.
    Type: Application
    Filed: January 23, 2001
    Publication date: June 5, 2003
    Inventors: Kei Murayama, Mitsutoshi Higashi, Hideaki Sakaguchi, Hiroko Koike
  • Publication number: 20030102547
    Abstract: In a semiconductor device including an insulating core substrate, a plurality of layers of wiring patterns on the core substrate and insulating layers interposed between the wiring patterns, each adjacent pair of the wiring patterns being electrically connected through a conductor portion penetrating through the insulating layer interposed between them, each of the insulating layers is formed integrally, semiconductor chips thinner than one layer of the insulating layer are mounted into at least one of the insulating layers, and the semiconductor chips are electrically connected to one layer of the wiring pattern of one insulating layer adjacent on the side of the core substrate.
    Type: Application
    Filed: January 2, 2003
    Publication date: June 5, 2003
    Inventors: Mitsutoshi Higashi, Kei Murayama, Hideaki Sakaguchi, Hiroko Koike