Patents by Inventor Hirokuni Yano

Hirokuni Yano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks
    Patent number: 11960719
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: October 27, 2022
    Date of Patent: April 16, 2024
    Assignee: Kioxia Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • MEMORY SYSTEM AND CONTROL METHOD THEREOF
    Publication number: 20240111416
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: December 7, 2023
    Publication date: April 4, 2024
    Applicant: Kioxia Corporation
    Inventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO
  • Memory system and control method thereof
    Patent number: 11893237
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: February 3, 2022
    Date of Patent: February 6, 2024
    Assignee: Kioxia Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS
    Publication number: 20230042619
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: October 27, 2022
    Publication date: February 9, 2023
    Applicant: Kioxia Corporation
    Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
  • Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks
    Patent number: 11513682
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: October 29, 2020
    Date of Patent: November 29, 2022
    Assignee: Kioxia Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • Storage device and method of controlling storage device
    Patent number: 11416372
    Abstract: A storage device includes a hardware random number generator configured to generate a random number; a first memory; and a controller configured to control the hardware random number generator and the first memory. The controller is configured to: obtain the random number generated by the hardware random number generator after the storage device is powered up; obtain a first trace log of the storage device; and store, into the first memory, a log resulting from appending the obtained random number to the first trace log, as a second trace log.
    Type: Grant
    Filed: August 19, 2020
    Date of Patent: August 16, 2022
    Assignee: Kioxia Corporation
    Inventors: Ryuji Nishikubo, Hirokuni Yano
  • MEMORY SYSTEM AND CONTROL METHOD THEREOF
    Publication number: 20220155960
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: February 3, 2022
    Publication date: May 19, 2022
    Applicant: Kioxia Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Memory system and control method thereof
    Patent number: 11287975
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: December 30, 2019
    Date of Patent: March 29, 2022
    Assignee: KIOXIA CORPORATION
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • STORAGE DEVICE AND METHOD OF CONTROLLING STORAGE DEVICE
    Publication number: 20210294526
    Abstract: A storage device includes a hardware random number generator configured to generate a random number; a first memory; and a controller configured to control the hardware random number generator and the first memory. The controller is configured to: obtain the random number generated by the hardware random number generator after the storage device is powered up; obtain a first trace log of the storage device; and store, into the first memory, a log resulting from appending the obtained random number to the first trace log, as a second trace log.
    Type: Application
    Filed: August 19, 2020
    Publication date: September 23, 2021
    Applicant: Kioxia Corporation
    Inventors: Ryuji NISHIKUBO, Hirokuni YANO
  • SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS
    Publication number: 20210042034
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: October 29, 2020
    Publication date: February 11, 2021
    Applicant: Toshiba Memory Corporation
    Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
  • Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks
    Patent number: 10845992
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: March 26, 2019
    Date of Patent: November 24, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • MEMORY SYSTEM AND CONTROL METHOD THEREOF
    Publication number: 20200133496
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: December 30, 2019
    Publication date: April 30, 2020
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO
  • Memory system and control method thereof
    Patent number: 10558360
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: February 11, 2020
    Assignee: Toshiba Memory Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS
    Publication number: 20190220197
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: March 26, 2019
    Publication date: July 18, 2019
    Applicant: Toshiba Memory Corporation
    Inventors: Hirokuni YANO, Shinichi KANNO, Toshikatsu HIDA, Hidenori MATSUZAKI, Kazuya KITSUNAI, Shigehiro ASANO
  • Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks
    Patent number: 10248317
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: June 8, 2017
    Date of Patent: April 2, 2019
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • MEMORY SYSTEM AND CONTROL METHOD THEREOF
    Publication number: 20180165011
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: February 13, 2018
    Publication date: June 14, 2018
    Applicant: Toshiba Memory Corporation
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • Memory system and control method thereof
    Patent number: 9933941
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Grant
    Filed: September 20, 2016
    Date of Patent: April 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventors: Kazuya Kitsunai, Shinichi Kanno, Hirokuni Yano, Toshikatsu Hida, Junji Yano
  • SEMICONDUCTOR STORAGE DEVICE WITH VOLATILE AND NONVOLATILE MEMORIES TO ALLOCATE BLOCKS TO A MEMORY AND RELEASE ALLOCATED BLOCKS
    Publication number: 20170269843
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Application
    Filed: June 8, 2017
    Publication date: September 21, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: HIROKUNI YANO, SHINICHI KANNO, TOSHIKATSU HIDA, HIDENORI MATSUZAKI, KAZUYA KITSUNAI, SHIGEHIRO ASANO
  • Semiconductor storage device with volatile and nonvolatile memories to allocate blocks to a memory and release allocated blocks
    Patent number: 9703486
    Abstract: A semiconductor storage device includes a first memory area configured in a volatile semiconductor memory, second and third memory areas configured in a nonvolatile semiconductor memory, and a controller which executes following processing. The controller executes a first processing for storing a plurality of data by the first unit in the first memory area, a second processing for storing data outputted from the first memory area by a first management unit in the second memory area, and a third processing for storing data outputted from the first memory area by a second management unit in the third memory area.
    Type: Grant
    Filed: August 10, 2015
    Date of Patent: July 11, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hirokuni Yano, Shinichi Kanno, Toshikatsu Hida, Hidenori Matsuzaki, Kazuya Kitsunai, Shigehiro Asano
  • MEMORY SYSTEM AND CONTROL METHOD THEREOF
    Publication number: 20170010818
    Abstract: A memory system includes a nonvolatile memory including a plurality of blocks as data erase units, a measuring unit which measures an erase time at which data of each block is erased, and a block controller which writes data supplied from at least an exterior into a first block which is set in a free state and whose erase time is oldest.
    Type: Application
    Filed: September 20, 2016
    Publication date: January 12, 2017
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya KITSUNAI, Shinichi KANNO, Hirokuni YANO, Toshikatsu HIDA, Junji YANO