Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.

Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.

Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.

Abstract: A solid-state imaging device includes: a semiconductor substrate; a pixel unit formed on the semiconductor substrate; and a peripheral circuit unit formed on the semiconductor substrate, at a periphery of the pixel unit, in which the pixel unit includes: a photoelectric conversion film which converts incident light into charges; and a floating diffusion which holds the charges, the peripheral circuit unit includes a transistor including a gate electrode and two source and drain diffusion regions, and the two source and drain diffusion regions have a higher impurity concentration than an impurity concentration of the floating diffusion.

Abstract: A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1<0.5s.

Abstract: A semiconductor device includes a first and a second MIS transistor. The first and second MIS transistors include a first and a second gate electrode formed on a first and a second active region with a first and a second gate insulating film being formed therebetween, first and second sidewalls including a first and a second inner sidewall formed on side surfaces of the first and second gate electrodes and having an L-shaped cross-section, and first and second source/drain regions formed in the first and second active regions laterally outside the first and second sidewalls. The first source/drain regions include a silicon compound layer formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region. A width of the first inner sidewall is smaller than a width of the second inner sidewall.

Abstract: A semiconductor device includes a first-conductivity-type first MIS transistor and a second-conductivity-type second MIS transistor. The first and second MIS transistors include a first and a second gate insulating film formed on a first and a second active region surrounded by a separation region of a semiconductor substrate, and a first and a second gate electrode formed on the first and second gate insulating films. The first and second gate insulating films are separated from each other on a first separation region of the separation region. A distance s between first ends of the first and second active regions facing each other with the first separation region being interposed therebetween, and a protrusion amount d1 from the first end of the first active region to a first end of the first gate insulating film located on the first separation region establish a relationship d1<0.5 s.

Abstract: A first source/drain region is formed outside a first insulating sidewall spacer, as viewed from a first gate electrode, in a semiconductor substrate. A second source/drain region is formed outside a second insulating sidewall spacer, as viewed from a second gate electrode, in the semiconductor substrate. The second source/drain region includes a silicon mixed-crystal layer. The second gate electrode has a lower height than the first gate electrode.

Abstract: A semiconductor device includes a first and a second MIS transistor. The first and second MIS transistors include a first and a second gate electrode formed on a first and a second active region with a first and a second gate insulating film being formed therebetween, first and second sidewalls including a first and a second inner sidewall formed on side surfaces of the first and second gate electrodes and having an L-shaped cross-section, and first and second source/drain regions formed in the first and second active regions laterally outside the first and second sidewalls. The first source/drain regions include a silicon compound layer formed in trenches provided in the first active region and causes a first stress in a gate length direction of a channel region in the first active region. A width of the first inner sidewall is smaller than a width of the second inner sidewall.

Abstract: A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.

Abstract: A memory cell array of a NOR type flash memory is constructed by arranging memory cell transistors in a matrix, each of the memory cell transistors includes a contact connecting a semiconductor substrate to an overlayer wire. Columns of the memory cell transistors are isolated from one another by shallow trench isolations. The height of top surface of a filling oxide film in the shallow trench isolation which is adjacent to each drain contact is equal to that of top surface of the drain region. The top surface of a filling oxide film in the shallow trench isolation which is adjacent to each channel region is higher than a top surface of the semiconductor substrate in the channel region.

Abstract: A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.

Abstract: A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.

Abstract: The semiconductor device includes: a first MIS transistor formed on a first region of a first conductivity type in a semiconductor substrate; and a second MIS transistor formed on a second region of a second conductivity type in the semiconductor substrate. The first MIS transistor has a first gate insulating film and a first gate electrode formed on the first region, first sidewalls formed on the side faces of the first gate electrode, and first source/drain regions made of silicon formed in portions of the first region. The second MIS transistor has a second gate insulating film and a second gate electrode formed on the second region, second sidewalls formed on the side faces of the second gate electrode, and second source/drain regions including silicon germanium formed in portions of the second region. The second sidewalls are smaller in height than the first sidewalls.

Abstract: A semiconductor device includes an n-type MIS transistor and a p-type MIS transistor. The n-type MIS transistor includes a first gate electrode formed on a first active region and a first sidewall formed on the side face of the first gate electrode. The p-type MIS transistor includes a second gate electrode formed on a second active region, a second sidewall formed on the side face of the second gate electrode and strain layers formed in the second active region. The second sidewall has a smaller thickness than the first sidewall.

Abstract: A semiconductor device has a transistor of a first conductivity type formed on a semiconductor substrate and having a first gate insulating film and a first gate electrode and a transistor of a second conductivity type having a second gate insulating film and a second gate electrode. The first gate electrode is a metal gate electrode having a metal film and the second gate electrode is a fully-silicided gate electrode made of a silicide film.

Abstract: A memory cell array of a NOR type flash memory is constructed by arranging memory cell transistors in a matrix, each of the memory cell transistors includes a contact connecting a semiconductor substrate to an overlayer wire. Columns of the memory cell transistors are isolated from one another by shallow trench isolations. The height of top surface of a filling oxide film in the shallow trench isolation which is adjacent to each drain contact is equal to that of top surface of the drain region. The top surface of a filling oxide film in the shallow trench isolation which is adjacent to each channel region is higher than a top surface of the semiconductor substrate in the channel region.

Abstract: A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.

Abstract: A semiconductor memory device, including a first memory cell having a first gate electrode, a first diffusion layer, and a second diffusion layer; a first contact layer connected to the first diffusion layer of the first memory cell; a second contact layer connected to the first contact layer; a second memory cell having a second gate electrode, a third diffusion layer and a fourth diffusion layer, the second gate electrode of the second memory cell electrically connected to the first gate electrode of the first memory cell, the first and second memory cells arranged in a direction perpendicular to the first bit line; and a conductive layer commonly connected to the second diffusion layer of the first memory cell and the fourth diffusion layer of the second memory cell, a height of the conductive layer substantially being coplanar with a height of the first contact layer.

Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.