Patents by Inventor Hiromasa Fujimoto
Hiromasa Fujimoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20050161745Abstract: An NMIS gate implantation layer is generated by a method in which mask data of a P-type well implantation layer are added to mask data obtained by subtracting mask data of an NMIS-SD implantation layer and PMIS-SD implantation layer from mask data of an N-type well implantation layer. In a CMOS device fabricating process, ions are implanted into a polysilicon film by using the NMIS gate implantation layer, resulting in reduction in the total numbers of PN junctions and non-doped regions in a gate polysilicon film.Type: ApplicationFiled: January 5, 2005Publication date: July 28, 2005Inventors: Tokuhiko Tamaki, Hiromasa Fujimoto, Takatoshi Yasui, Takehiro Hirai
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Publication number: 20050051837Abstract: Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100° C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.Type: ApplicationFiled: October 18, 2004Publication date: March 10, 2005Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Hiromasa Fujimoto, Fumihiko Noro, Masataka Kusumi
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Patent number: 6830973Abstract: Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100° C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.Type: GrantFiled: September 11, 2002Date of Patent: December 14, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiromasa Fujimoto, Fumihiko Noro, Masataka Kusumi
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Publication number: 20040246803Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.Type: ApplicationFiled: July 13, 2004Publication date: December 9, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Nobuyo Sugiyama, Hiromasa Fujimoto, Shinji Odanaka, Seiki Ogura
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Patent number: 6828621Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: GrantFiled: October 7, 2003Date of Patent: December 7, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Patent number: 6803623Abstract: The nonvolatile semiconductor memory device has a floating gate electrode that is formed on the semiconductor region and stores carriers injected from the semiconductor region and a control gate electrode that controls the quantity of stored carriers by applying a predetermined voltage to the floating gate electrode. The source region is formed in the semiconductor region on one of side regions of the floating gate electrode and control gate electrode, while the drain region is formed on the other of the side regions thereof. The drain region creates an electric field from which the carriers injected into the floating gate electrode are subject to an external force having an element directed from the semiconductor region to the floating gate electrode.Type: GrantFiled: December 6, 2001Date of Patent: October 12, 2004Assignees: Matsushita Electric Industrial Co., Ltd., Halo LSI Design and Device Technologies Inc.Inventors: Nobuyo Sugiyama, Shinji Odanaka, Hiromasa Fujimoto, Seiki Ogura
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Patent number: 6784040Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: GrantFiled: March 7, 2003Date of Patent: August 31, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Patent number: 6770517Abstract: In a silicon layer formed on an insulator layer, a lattice defect region is formed to be adjacent to a channel region and source/drain regions, and the lower part of the channel region functions as a high-concentration channel region. The holes of hole-electron pairs generated in the channel region are eliminated by recombination in the lattice defect region, thereby suppressing the bipolar operation resulting from the accumulation of holes and increasing the source/drain breakdown voltage. The threshold value of a parasitic transistor is increased by the high-concentration channel region so as to reduce the leakage current in the OFF state. Alternatively, the holes may be moved to the source region to disappear therein by providing, instead of the lattice defect region, a high-concentration diffusion layer constituting and operating as a pn diode between the channel and source regions.Type: GrantFiled: December 28, 2001Date of Patent: August 3, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Hiroaki Nakaoka, Hiromasa Fujimoto, Atsushi Hori, Takashi Uehara, Takehiro Hirai
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Patent number: 6770931Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.Type: GrantFiled: February 14, 2003Date of Patent: August 3, 2004Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nobuyo Sugiyama, Hiromasa Fujimoto, Shinji Odanaka, Seiki Ogura
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Publication number: 20040079985Abstract: A semiconductor memory device having a gate electrode and a diffusion layer, comprising a plurality of memory cells each of which including the gate electrode and the diffusion layers; a first contact layer connected to one of the diffusion layer of the memory cell; a second contact layer connected to the first contact layer; a bit line connected to the second contact layer; and a conductive layer connected to at least two of the diffusion layers that are other than the diffusion layer connected to the first contact layer, at least two of the diffusion layers being arranged in a direction vertical to the bit line, a height of the conductive layer substantially being same as a height of the first contact layer.Type: ApplicationFiled: June 25, 2003Publication date: April 29, 2004Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Keisuke Yonehama, Eiji Sakagami, Hiromasa Fujimoto, Naoki Koido
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Publication number: 20040071024Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: ApplicationFiled: October 7, 2003Publication date: April 15, 2004Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Patent number: 6642572Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: GrantFiled: March 7, 2003Date of Patent: November 4, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Publication number: 20030173616Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: ApplicationFiled: March 7, 2003Publication date: September 18, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Publication number: 20030141540Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: ApplicationFiled: March 7, 2003Publication date: July 31, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Publication number: 20030122180Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.Type: ApplicationFiled: February 14, 2003Publication date: July 3, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Nobuyo Sugiyama, Hiromasa Fujimoto, Shinji Odanaka, Seiki Ogura
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Patent number: 6545312Abstract: A nonvolatile semiconductor memory device has a protective insulating film deposited on each of the side surfaces of a control gate electrode to protect the control gate electrode during the formation of a floating gate electrode, the floating gate electrode opposed to one of the side surfaces of the control gate electrode with the protective insulating film interposed therebetween so as to be capacitively coupled to the control gate electrode, a tunnel insulating film formed between the floating gate electrode and the semiconductor substrate, a drain region formed in a region of the semiconductor substrate containing a portion underlying the floating gate electrode, and a source region formed in a region of the semiconductor substrate opposite to the drain region relative to the control gate electrode.Type: GrantFiled: July 3, 2001Date of Patent: April 8, 2003Assignees: Matsushita Electric Industrial Co., Ltd., Halo LSI Design and Device Technologies Inc.Inventors: Masataka Kusumi, Fumihiko Noro, Hiromasa Fujimoto, Akihiro Kamada, Shinji Odanaka, Seiki Ogura
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Patent number: 6538275Abstract: A nonvolatile semiconductor memory device according to the present invention has a control gate electrode which is formed on the upper stage of a stepped portion formed in the principal surface of a substrate with a first insulating film interposed therebetween and a floating gate electrode which is formed to cover up the stepped portion, capacitively coupled to the side surface of the control gate electrode closer to the stepped portion with a second insulating film interposed therebetween, and opposed to the lower stage of the stepped portion with a third insulating film serving as a tunnel film interposed therebetween.Type: GrantFiled: July 12, 2001Date of Patent: March 25, 2003Assignee: Matsushita Electric Industrial Co., Ltd.Inventors: Nobuyo Sugiyama, Hiromasa Fujimoto, Shinji Odanaka, Seiki Ogura
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Publication number: 20030047775Abstract: Using a rapid thermal oxidation device, the top and side surfaces of a floating gate electrode are oxidized by In Situ Steam Generation (ISSG), wherein oxygen to which about 0.5 to 33% hydrogen has been added is introduced directly into a chamber with a temperature of approximately 900 to 1100° C. and a pressure of approximately 1,000 to 2,000 Pa, in order to generate water vapor from the introduced hydrogen and oxygen on a heated semiconductor substrate. Thus, an insulating film made of silicon oxide is formed on the surface of the floating gate electrode.Type: ApplicationFiled: September 11, 2002Publication date: March 13, 2003Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.Inventors: Hiromasa Fujimoto, Fumihiko Noro, Masataka Kusumi
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Publication number: 20020145162Abstract: A non-volatile semiconductor storage device includes a semiconductor substrate provided with a step portion in an upper portion thereof, and having a first region that is an upper level of the step portion and a second region that is a lower level thereof, a control gate electrode formed on the first region of the semiconductor substrate via a gate insulating film, and a floating gate electrode formed on the side face of the control gate electrode on the side of the step portion and on the step portion via an insulating film. The side face of the step portion forms an obtuse angle with respect to the upper surface of the second region, and the insulating film has a substantially uniform thickness on the step portion.Type: ApplicationFiled: February 5, 2002Publication date: October 10, 2002Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.,Inventors: Akihiro Kamada, Hiromasa Fujimoto, Kenji Okada, Seiki Ogura
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Publication number: 20020074583Abstract: The nonvolatile semiconductor memory device has a floating gate electrode that is formed on the semiconductor region and stores carriers injected from the semiconductor region and a control gate electrode that controls the quantity of stored carriers by applying a predetermined voltage to the floating gate electrode. The source region is formed in the semiconductor region on one of side regions of the floating gate electrode and control gate electrode, while the drain region is formed on the other of the side regions thereof. The drain region creates an electric field from which the carriers injected into the floating gate electrode are subject to an external force having an element directed from the semiconductor region to the floating gate electrode.Type: ApplicationFiled: December 6, 2001Publication date: June 20, 2002Applicant: Matsushita Electric Industrial Co., Ltd.Inventors: Nobuyo Sugiyama, Shinji Odanaka, Hiromasa Fujimoto, Seiki Ogura