Abstract: A data transferring method for a nonvolatile memory composed of a flash memory. The flash memory allows a gaplessly read process to be performed unless a transfer error takes place. The flash memory comprises a first shift register, a second shift register, and a switching circuit. The first shift register stores data of the first half area of one page for a data re-transfer process in the case that a transfer error takes place. The second shift register stores data of the second half area of one page for a data re-transfer process in the case that a transfer error takes place. The switching circuit switches between output data of a memory cell array and output data of the first and second shift registers. As a result, data can be transferred at the logically maximum speed. In addition, a transfer error is detected page by page. When a transfer error is detected, the data re-transfer process is performed using the shift registers. Thus, the throughput can be suppressed from deteriorating.

Abstract: A data transferring method for a nonvolatile memory composed of a flash memory is disclosed. The flash memory allows a gaplessly read process to be performed unless a transfer error takes place. The flash memory comprises a first shift register, a second shift register, and a switching circuit. The first shift register stores data of the first half area of one page for a data re-transfer process in the case that a transfer error takes place. The second shift register stores data of the second half area of one page for a data re-transfer process in the case that a transfer error takes place. The switching circuit switches between output data of a memory cell array and output data of the first and second shift registers. As a result, data can be transferred at the logically maximum speed. In addition, a transfer error is detected page by page. When a transfer error is detected, the data re-transfer process is performed using the shift registers. Thus, the throughput can be suppressed from deteriorating.

Abstract: A non-volatile semiconductor memory capable of dealing with eight levels and a method of writing data therein, which can shorten the writing time and perform verify read and normal read operations at a high speed by connecting a bit line to a supply source of a voltage in accordance with latch data of a latch circuit after charging all bit lines at a power source voltage level before a write operation, and by performing the write operations in parallel.

Abstract: A nonvolatile semiconductor storage device is disclosed. The device has memory cells for storing data corresponding to threshold voltages that vary corresponding to the amount of electric charge stored in electric charge storing portions, the amount of electric charge varying corresponding to voltages supplied to word lines and bit lines, multi-value data of n bits (where n≧2) being written in parallel and page by page to the memory cells. The device comprises a write controlling means for supplying a voltage for word lines as a pulse signal to memory cells and controlling the pulse width of the effective voltage of word lines corresponding to a substantial write time period of data written to the memory cells.

Abstract: In a non-volatile semiconductor memory device of a flash type for recording multivalue data into memory cells, a control is made such that a word line voltage is set in accordance with a distribution state of a threshold voltage at the time of verification of data after the writing, a precharge of a bit line is controlled in accordance with data latched in a latch circuit, whether a threshold value of the memory cell exceeds a voltage applied to word line or not is detected depending on whether a current sufficiently flows in the memory cell or not, a state of the latch circuit is specified by a detection output, and when data is sufficiently written, predetermined data is set into the latch circuit. At the time of reading, a control is made so that a word line voltage is set in accordance with the distribution state of the threshold voltage, the state of the latch circuit is specified depending on whether a current sufficiently flows in the memory cell or not, and the read data is set into the latch circuit.

Abstract: A nonvolatile semiconductor memory device having a memory cell in which an amount of charge stored in a charge storage unit changes according to a voltage supplied to a word line and a bit line, a threshold voltage changes according to that change, and data of a value according to the threshold voltage is stored, and writing trinary or more multi-bit data into memory cells in units of pages, provided with a precharging means for precharging all bit lines to a predetermined voltage before the write operation and a write control circuit having a latch circuit by which the write data is latched, making the bit line selected in accordance with an address discharge in accordance with the latch data, and performing write operations in parallel.

Abstract: A nonvolatile semiconductor memory device capable of improving a reliability of a spare region, capable of improving the reliability of a data region in accordance with a method of use, and capable of realizing a function of an additional writing as a multi-level memory, and an IC memory card using the same, provided with a data region capable of storing 4-level and binary data; a spare region capable of storing binary data; data region use decoders for supplying a drive voltage to the data region; spare region use decoders and for supplying the drive voltage to the spare region; a latch circuit for transferring data with the data region in accordance with the number of levels of the multi-level data to be stored in the data region and stopping the supply of the drive voltage of the sub decoder when the transfer of data is normally completed; and a latch circuit for transferring data with the spare region and stopping the supply of the drive voltage of the sub decoder when the transfer of data is normally com

Abstract: In a flash EEPROM where erasing and verifying operations are repeated until the threshold voltages of memory cells reach a predetermined value, a negative voltage is applied, at the time of verification, to the control gate electrode of each cell on a nonselected row, so that the verification is rendered possible despite the existence of any overerased memory cell in the nonselected area, and then the overerased cell is rewritten to be released from the overerased state, whereby the threshold voltage distribution of the memory cells is settable in a narrow range. And by the provision of a means for converting an external designated address to an internal chip address, the storage area designated by the external address is shifted or circulated in the chip every time the data is erased, so that the number of repeatable reprogramming actions is increased apparently in the flash EEPROM.

Abstract: In a flash EEPROM where erasing and verifying operations are repeated until the threshold voltages of memory cells reach a predetermined value, a negative voltage is applied, at the time of verification, to the control gate electrode of each cell on a nonselected row, so that the verification is rendered possible despite the existence of any overerased memory cell in the nonselected area, and then the overerased cell is rewritten to be released from the overerased state, whereby the threshold voltage distribution of the memory cells is settable in a narrow range. And by the provision of a means for converting an external designated address to an internal chip address, the storage area designated by the external address is shifted or circulated in the chip every time the data is erased, so that the number of repeatable reprogramming actions is increased apparently in the flash EEPROM.

Abstract: In a nonvolatile semiconductor memory device having a memory array of a NAND structure, threshold voltages of the word line voltage set at the time of reading are set to V.sub.WL00, V.sub.WL01, and V.sub.WL10, and one V.sub.WL10 among the threshold voltages is set to the negative voltage. By this, it becomes possible to set the threshold voltage distribution width of the memory transistor and the interval between one data and the next wider. As a result, writing control becomes easier and the disturbance/retention characteristics can be enhanced.

Abstract: A non-volatile memory device which enables use of a folded bit line system includes odd and even main bit lines, a plurality of sub-bit lines connected to the main bit lines through selection gates. Conductive and non-conductive states of the selection gate connecting to the odd main bit line and the selection gate connecting to the even main bit line are controlled by different selection signal lines so that the odd main bit line and the even bit line are operated selectively.

Abstract: A semiconductor nonvolatile memory device which enables shortening of the time of the bit verification operation and thus high speed reading operations, including a first memory cell array connected to a first bit line, a second memory cell array connected to a second bit line, a first transistor operatively connecting the first bit line and a first node, a second transistor operatively connecting the second bit line and a second node, a precharging circuit for precharging the first and second bit lines, and an equalizing circuit for equalizing the sense amplifier, wherein, at the time of a verification read operation, the gate electrode of the transistor connected to the bit line on the reference side is given as input a control signal set to a level not more than a voltage comprised of the precharge voltage of that bit line plus the threshold voltage of that transistor.

Abstract: The present invention permits the re-writing of data selectively only in cells in which data is written incompletely. A non-volatile memory is set in a re-write mode when a bit line voltage is high (H). In the re-write mode, a sense amplifier and a selected cell are activated. Because latched data in the sense amplifier is high (H), the electrons in the selected cell produce FN-tunneling, thereby writing data "0" in the selected cell. Because the bit line level of voltage (BLR) of the other cells in which data is written completely is reduced to a low level (L), the latched data in the sense amplifier is reduced to a low level (L). Accordingly, when the word line of a selected cell is connected to other cells in which data is written completely, because data is prevented from being re-written in said other cells, the threshold levels of the various cells remain equal and do not become distributed broadly.