Patents by Inventor Hiromi Shigihara

Hiromi Shigihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10818620
    Abstract: In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: October 27, 2020
    Assignee: Renesas Electronics Corporation
    Inventors: Hiromi Shigihara, Hiroshi Tsukamoto, Akira Yajima
  • Patent number: 10157974
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a first insulating film formed on the main surface, a first coil formed on the first insulating film, a second insulating film formed on the first coil and having a first main surface and first side surfaces continuous with the first main surface, a third insulating film formed on the first main surface of the second insulating film and having a second main surface and second side surfaces continuous with the second main surface, and a second coil formed on the second main surface of the third insulating film. The second insulating film and the third insulating film are formed as a laminated insulating film together. A thickness of the second coil is greater than a thickness of the first coil in a thickness direction of the semiconductor substrate.
    Type: Grant
    Filed: October 31, 2017
    Date of Patent: December 18, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao Shigihara
  • Patent number: 10128129
    Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.
    Type: Grant
    Filed: June 13, 2017
    Date of Patent: November 13, 2018
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiko Akiba, Hiromi Shigihara, Kei Yajima
  • Publication number: 20180069073
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface, a first insulating film formed on the main surface, a first coil formed on the first insulating film, a second insulating film formed on the first coil and having a first main surface and first side surfaces continuous with the first main surface, a third insulating film formed on the first main surface of the second insulating film and having a second main surface and second side surfaces continuous with the second main surface, and a second coil formed on the second main surface of the third insulating film. The second insulating film and the third insulating film are formed as a laminated insulating film together. A thickness of the second coil is greater than a thickness of the first coil in a thickness direction of the semiconductor substrate.
    Type: Application
    Filed: October 31, 2017
    Publication date: March 8, 2018
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao SHIGIHARA
  • Patent number: 9818815
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view.
    Type: Grant
    Filed: December 7, 2015
    Date of Patent: November 14, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao Shigihara
  • Publication number: 20170278722
    Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.
    Type: Application
    Filed: June 13, 2017
    Publication date: September 28, 2017
    Inventors: Toshihiko AKIBA, Hiromi SHIGIHARA, Kei YAJIMA
  • Patent number: 9711377
    Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.
    Type: Grant
    Filed: October 18, 2015
    Date of Patent: July 18, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Toshihiko Akiba, Hiromi Shigihara, Kei Yajima
  • Patent number: 9704805
    Abstract: To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.
    Type: Grant
    Filed: April 27, 2016
    Date of Patent: July 11, 2017
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hisao Shigihara, Hiromi Shigihara, Akira Yajima, Hiroshi Tsukamoto
  • Publication number: 20170005048
    Abstract: In a method of manufacturing a semiconductor device, a semiconductor chip has first and second pads, a passivation film formed such that respective parts of the first and second pads are exposed, a first surface-metal-layer provided on the part of the first pad and a part of the passivation film, and a second surface-metal-layer provided on the part of the second pad and another part of the passivation film. Respective wires are electrically connected to the first and second surface-metal-layers. The semiconductor chip and the respective wires are then sealed with a resin.
    Type: Application
    Filed: September 13, 2016
    Publication date: January 5, 2017
    Inventors: HIROMI SHIGIHARA, HIROSHI TSUKAMOTO, AKIRA YAJIMA
  • Patent number: 9466559
    Abstract: In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).
    Type: Grant
    Filed: September 12, 2011
    Date of Patent: October 11, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hiromi Shigihara, Hiroshi Tsukamoto, Akira Yajima
  • Publication number: 20160240484
    Abstract: To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.
    Type: Application
    Filed: April 27, 2016
    Publication date: August 18, 2016
    Inventors: Hisao SHIGIHARA, Hiromi SHIGIHARA, Akira YAJIMA, Hiroshi TSUKAMOTO
  • Patent number: 9343395
    Abstract: To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.
    Type: Grant
    Filed: June 24, 2013
    Date of Patent: May 17, 2016
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Hisao Shigihara, Hiromi Shigihara, Akira Yajima, Hiroshi Tsukamoto
  • Publication number: 20160133484
    Abstract: Provided is a semiconductor device with improved reliability that achieves the reduction in size. A semiconductor wafer is provided that has a first insulating member with an opening that exposes from which an upper surface of an electrode pad. Subsequently, after forming a second insulating member over a main surface of the semiconductor wafer, another opening is formed to expose the upper surface of the electrode pad. Then, a probe needle is brought into contact with the electrode pad, to write data in a memory circuit at the main surface of the semiconductor wafer. After covering the upper surface of the electrode pad with a conductive cover film, a relocation wiring is formed. In the Y direction, the width of the relocation wiring positioned directly above the electrode pad is equal to or smaller than the width of the opening formed in the first insulating member.
    Type: Application
    Filed: October 18, 2015
    Publication date: May 12, 2016
    Inventors: Toshihiko AKIBA, Hiromi SHIGIHARA, Kei YAJIMA
  • Publication number: 20160087025
    Abstract: A semiconductor device includes a semiconductor substrate having a main surface; a first coil formed on the main surface; a first insulating film formed over the first coil and having a first main surface; a second insulating film formed on the first main surface of the first insulating film and having a second main surface; and a second coil formed on the second main surface of the second insulating film, wherein the first main surface of the first insulating film has a first area on which the second insulating film is formed, and has a second area without the first area in a plan view, and wherein the second insulating film is surrounded with the second area in the plane view.
    Type: Application
    Filed: December 7, 2015
    Publication date: March 24, 2016
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao SHIGIHARA
  • Patent number: 9219108
    Abstract: A semiconductor device including a semiconductor substrate having a main surface; a first insulating layer formed on the main surface and having a first main surface, the first main surface including a first region and a second region without the first area; a first coil formed on the first region of the first insulating layer; a plurality of first wirings formed on the second region of the first insulating layer; a second insulating layer formed on the first coil and on the first wirings, the second insulating layer having a second main surface; a third insulating layer formed on the second main surface above the first region of the first insulating layer and having a third main surface; and a second coil formed on the third main surface of the third insulating layer.
    Type: Grant
    Filed: February 18, 2015
    Date of Patent: December 22, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao Shigihara
  • Publication number: 20150162395
    Abstract: A semiconductor device including a semiconductor substrate having a main surface; a first insulating layer formed on the main surface and having a first main surface, the first main surface including a first region and a second region without the first area; a first coil formed on the first region of the first insulating layer; a plurality of first wirings formed on the second region of the first insulating layer; a second insulating layer formed on the first coil and on the first wirings, the second insulating layer having a second main surface; a third insulating layer formed on the second main surface above the first region of the first insulating layer and having a third main surface; and a second coil formed on the third main surface of the third insulating layer.
    Type: Application
    Filed: February 18, 2015
    Publication date: June 11, 2015
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao Shigihara
  • Patent number: 8987861
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device has a laminated insulating film formed above a lower-layer inductor. This laminated insulating film includes a first polyimide film, and a second polyimide film formed on the first polyimide film and having a second step between the first polyimide film and the second polyimide film. An upper-layer inductor is formed on the laminated insulating film. Since such a laminated structure of the first and second polyimide films is adopted, the film thickness of the insulating film between the lower-layer and upper-layer inductors can be increased, so that withstand voltage can be improved. Further, the occurrence of a depression or peeling-off due to defective exposure can be reduced, and step disconnection of a Cu (copper) seed layer or a plating defect due to the step disconnection can also be reduced.
    Type: Grant
    Filed: December 13, 2013
    Date of Patent: March 24, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao Shigihara
  • Publication number: 20140175602
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device has a laminated insulating film formed above a lower-layer inductor. This laminated insulating film includes a first polyimide film, and a second polyimide film formed on the first polyimide film and having a second step between the first polyimide film and the second polyimide film. An upper-layer inductor is formed on the laminated insulating film. Since such a laminated structure of the first and second polyimide films is adopted, the film thickness of the insulating film between the lower-layer and upper-layer inductors can be increased, so that withstand voltage can be improved. Further, the occurrence of a depression or peeling-off due to defective exposure can be reduced, and step disconnection of a Cu (copper) seed layer or a plating defect due to the step disconnection can also be reduced.
    Type: Application
    Filed: December 13, 2013
    Publication date: June 26, 2014
    Applicant: Renesas Electronics Corporation
    Inventors: Takuo Funaya, Hiromi Shigihara, Hisao Shigihara
  • Publication number: 20140021618
    Abstract: To provide a semiconductor device having improved reliability by improving a coupling property between a semiconductor chip and a bonding wire. A redistribution layer is comprised of a Cu film, an Ni film, and a Pd film which have been formed successively from the side of a semiconductor substrate. The Pd film on the uppermost surface is used as an electrode pad and a bonding wire made of Cu is coupled to the upper surface of the Pd film. The thickness of the Pd film is made smaller than that of the Ni film and the thickness of the Ni film is made smaller than that of the Cu film. The Cu film, the Ni film, and the Pd film have the same pattern shape in a plan view.
    Type: Application
    Filed: June 24, 2013
    Publication date: January 23, 2014
    Inventors: Hisao SHIGIHARA, Hiromi SHIGIHARA, Akira YAJIMA, Hiroshi TSUKAMOTO
  • Publication number: 20130313708
    Abstract: In semiconductor integrated circuit devices for vehicle use, an aluminum pad on a semiconductor chip and an external device are coupled to each other by wire bonding using a gold wire for the convenience of mounting. Such a semiconductor integrated circuit device, however, causes a connection failure due to the interaction between aluminum and gold in use for a long time at a relatively high temperature (about 150 degrees C.). A semiconductor integrated circuit device can include a semiconductor chip as a part of the device, an electrolytic gold plated surface film (gold-based metal plated film) provided over an aluminum-based bonding pad on a semiconductor chip via a barrier metal film, and a gold bonding wire (gold-based bonding wire) for interconnection between the plated surface film and an external lead provided over a wiring board (wiring substrate).
    Type: Application
    Filed: July 27, 2013
    Publication date: November 28, 2013
    Applicant: Renesas Electronics Corporation
    Inventors: Hiromi SHIGIHARA, Hiroshi TSUKAMOTO, Akira YAJIMA