Patents by Inventor Hiromichi Enami
Hiromichi Enami has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20010015175Abstract: The object of the present invention is to provide a plasma processing apparatus wherein plasma is generated in process chamber to treat a sample. Said plasma processing apparatus is further characterized in that multiple closely packed through-holes are formed on the plate installed on the UHF antenna arranged opposite to the sample, an optical transmitter is installed almost in contact with the back of the through-holes, and an optical transmission means is arranged on the other end of said optical transmitter, thereby measuring optical information coming from the sample and plasma through optical transmitter and optical transmission means by means of an measuring instrument. No abnormal discharge or particle contamination occur to through-holes even in long-term discharge process, and no deterioration occurs to the optical performance at the end face of the optical transmitter.Type: ApplicationFiled: February 21, 2001Publication date: August 23, 2001Inventors: Toshio Masuda, Tatehito Usui, Mitsuru Suehiro, Hiroshi Kanekiyo, Hideyuki Yamamoto, Kazue Takahashi, Hiromichi Enami
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Patent number: 6169324Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: October 6, 1999Date of Patent: January 2, 2001Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 6127255Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions. The disclosed process includes forming insulating films over wiring lines including uppermost wiring lines, the uppermost wiring lines having gaps between adjacent uppermost wiring lines. The insulating films include forming a silicon oxide film over the wiring lines and in the gaps between adjacent uppermost wiring lines, and forming a silicon nitride film over the silicon oxide film, the silicon nitride film being formed by plasma chemical vapor deposition. The silicon oxide film is formed to have a thickness of at least one-half of the gap between adjacent uppermost wiring lines, with the silicon nitride film being thicker than the silicon oxide film.Type: GrantFiled: October 3, 1997Date of Patent: October 3, 2000Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5917211Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.Type: GrantFiled: November 25, 1997Date of Patent: June 29, 1999Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
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Patent number: 5811316Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: June 5, 1995Date of Patent: September 22, 1998Assignees: Hitachi. Ltd., Hitachi VLSI Engineering CorporationInventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5780882Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: June 1, 1995Date of Patent: July 14, 1998Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5739589Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: June 3, 1996Date of Patent: April 14, 1998Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5734188Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.Type: GrantFiled: July 1, 1996Date of Patent: March 31, 1998Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
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Patent number: 5646489Abstract: A plasma processing apparatus has a waveguide along which microwaves are propagated from a microwave generator to a plasma-forming region in a low-pressure processing chamber. The waveguide has a large cross-sectional area, to enable a large region of plasma to be achieved. Uniformity and stability of the plasma are improved by a mode restrictor which inhibits mixing of propagation modes which is otherwise liable to occur in a wide waveguide. The mode restrictor consists of electrically conductive dividers which divide the waveguide cross-section into an array of sub-guides before the plasma-forming region.Type: GrantFiled: May 2, 1995Date of Patent: July 8, 1997Assignee: Hitachi, Ltd.Inventors: Yutaka Kakehi, Yoshinao Kawasaki, Keizo Suzuki, Kazuo Nojiri, Hiromichi Enami, Tetsunori Kaji, Seiichi Watanabe, Yoshifumi Ogawa
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Patent number: 5557147Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: April 19, 1994Date of Patent: September 17, 1996Assignees: Hitachi, Ltd., Hitachi ULSI Engineering CorporationInventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5543336Abstract: A chamber 103 for introducing hydrogen without causing serious damage to a semiconductor wafer and a chamber 104 for eliminating the hydrogen introduced into the semiconductor wafer at relatively low temperature are installed at the succeeding stage of a plasma etching unit for effectively correcting the damage caused by plasma etching and ion implantation to a semiconductor substrate or an ion implanting unit. In order to introduce hydrogen into the semiconductor wafer without serious damage, a mixture of hydrocarbon gas and oxygen gas for accelerating the decomposition of the hydrocarbon gas is used for forming hydrogen radicals in a plasma and the hydrogen radicals are supplied to the semiconductor wafer at room temperature by a downstream system. The semiconductor wafer is heat-treated in an atmosphere of a vacuum or inactive gas in a temperature region of 200.degree.-500.degree. C. to eliminate the hydrogen introduced into the semiconductor wafer.Type: GrantFiled: November 25, 1994Date of Patent: August 6, 1996Assignee: Hitachi, Ltd.Inventors: Hiromichi Enami, Kiyomi Katsuyama, Masanori Katsuyama
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Patent number: 5433789Abstract: A plasma processing apparatus has a waveguide along which microwaves are propagated from a microwave generator to a plasma-forming region in a low-pressure processing chamber. The waveguide has a large cross-sectional area, to enable a large region of plasma to be achieved. Uniformity and stability of the plasma are improved by a mode restrictor which inhibits mixing of propagation modes which is otherwise liable to occur in a wide waveguide. The mode restrictor consists of electrically-conductive dividers which divide the waveguide cross-section into an array of sub-guides before the plasma-forming region.Type: GrantFiled: January 28, 1993Date of Patent: July 18, 1995Assignee: Hitachi, Ltd.Inventors: Yutaka Kakehi, Yoshinao Kawasaki, Keizo Suzuki, Kazuo Nojiri, Hiromichi Enami, Tetsunori Kaji, Seiichi Watanabe, Yoshifumi Ogawa
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Patent number: 5401356Abstract: The amount of dust particles deposited on a semiconductor wafer during plasma etching or CVD in manufacturing a semiconductor integrated circuit is decreased by second plasma generating electrode 28 disposed around a lower electrode 15 in a plasma etching chamber 4a. High frequency voltage is applied to the second plasma generating electrode 18 just before the stop of plasma discharge to form a sub-plasma of high density along the outer periphery of the lower electrode 15, there is formed a sub-potential distribution acting to push out negatively charged dust particles stagnating near the main surface of a semiconductor substrate 7 toward the outer periphery of the wafer. The negatively charged dust particles thus pushed out from the vicinity of the main surface of the wafer 7 are moved to the second plasma generating electrode 28 and exhausted by a vacuum pump through an exhaust port 25.Type: GrantFiled: July 31, 1992Date of Patent: March 28, 1995Assignee: Hitachi, Ltd.Inventors: Hiromichi Enami, Kiyomi Yagi, Masanori Katsuyama, Akihiko Konno
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Patent number: 5352324Abstract: Disclosed is an etching method and an apparatus for performing an etching by alternately and repeatedly switching an average thickness of an ion sheath and an average energy of etching ions between two different values. Since the etchant absorption to the surface of an article to be etched and the etching by ions are effectively performed, it is possible to reduce the influence of an aspect ratio on an etching depth, and hence to perform the etching with an equal depth even if the width of the opening is changed.Type: GrantFiled: October 18, 1993Date of Patent: October 4, 1994Assignee: Hitachi, Ltd.Inventors: Yasushi Gotoh, Tokuo Kure, Hiroshi Kawakami, Masanori Katsuyama, Kiyomi Yagi, Hiromichi Enami
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Patent number: 5331191Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: September 30, 1992Date of Patent: July 19, 1994Assignees: Hitachi, Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 5264712Abstract: A semiconductor integrated circuit comprising first n-channel MISFETs constituting the memory cells of a storage system, second n-channel MISFETs constituting the peripheral circuits of the storage system, and third n-channel MISFETs constituting the output circuit among the peripheral circuits. The respective threshold voltages of the first n-channel MISFETs, the second n-channel MISFETs and the third n-channel MISFETs are decreased in that order when the respective gate lengths of those MISFETs are substantially the same.Type: GrantFiled: May 7, 1992Date of Patent: November 23, 1993Assignee: Hitachi, Ltd.Inventors: Jun Murata, Yoshitaka Tadaki, Hiroko Kaneko, Toshihiro Sekiguchi, Hiroyuki Uchiyama, Hisashi Nakamura, Toshio Maeda, Osamu Kasahara, Hiromichi Enami, Atsushi Ogishima, Masaki Nagao, Michimasa Funabashi, Yasuo Kiguchi, Masayuki Kojima, Atsuyoshi Koike, Hiroyuki Miyazawa, Masato Sadaoka, Kazuya Kadota, Tadashi Chikahara, Kazuo Nojiri, Yutaka Kobayashi
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Patent number: 5202275Abstract: Herein disclosed is a semiconductor integrated circuit device fabricating process for forming MISFETs over the principal surface in those active regions of a substrate, which are surrounded by inactive regions formed of an element separating insulating film and channel stopper regions, comprising: the step of for forming a first mask by a non-oxidizable mask and an etching mask sequentially over the principal surface of the active regions of the substrate; the step of forming a second mask on and in self-alignment with the side walls of the first mask by a non-oxidizable mask thinner than the non-oxidizable mask of the first mask and an etching mask respectively; the step of etching the principal surface of the inactive regions of the substrate by using the first mask and the second mask; the step of forming the element separating insulating film over the principal surface of the inactive regions of the substrate by an oxidization using the first mask and the second mask; and the step of forming the channel sType: GrantFiled: March 20, 1990Date of Patent: April 13, 1993Assignees: Hitachi Ltd., Hitachi VLSI Engineering Corp.Inventors: Jun Sugiura, Osamu Tsuchiya, Makoto Ogasawara, Fumio Ootsuka, Kazuyoshi Torii, Isamu Asano, Nobuo Owada, Mitsuaki Horiuchi, Tsuyoshi Tamaru, Hideo Aoki, Nobuhiro Otsuka, Seiichirou Shirai, Masakazu Sagawa, Yoshihiro Ikeda, Masatoshi Tsuneoka, Toru Kaga, Tomotsugu Shimmyo, Hidetsugu Ogishi, Osamu Kasahara, Hiromichi Enami, Atsushi Wakahara, Hiroyuki Akimori, Sinichi Suzuki, Keisuke Funatsu, Yoshinao Kawasaki, Tunehiko Tubone, Takayoshi Kogano, Ken Tsugane
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Patent number: 4949162Abstract: A multilayer semiconductor integrated circuit having a plurality of wiring layers in which at least the lines of a lower layer are extended on wiring channel regions arranged in a grid. Dummy pedestals are formed of the same conductive layer as that forming the lines of the lower layer and are arranged in the intersecting areas of the wiring channel regions where none of the lines of the lower layer is placed. A method of manufacturing such a semiconductor integrated circuit comprises steps of preparing dummy pedestal layout data for arranging the dummy pedestals in all the intersecting areas of the wiring channel regions and line layout data for forming the lines of the lower layer on predetermined wiring channels among all the wiring channel regions, and combining the dummy pedestal layout data and the line layout data by logical sum (OR).Type: GrantFiled: June 3, 1988Date of Patent: August 14, 1990Assignee: Hitachi, Ltd.Inventors: Yoichi Tamaki, Kiyoji Ikeda, Toru Nakamura, Akihisa Uchida, Toru Koizumi, Hiromichi Enami, Satoru Isomura, Shinji Nakajima, Katsumi Ogiue, Kaoru Ohgaya