Patents by Inventor Hiromichi Godo

Hiromichi Godo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10411013
    Abstract: To provide a semiconductor device with large storage capacity and low power consumption. The semiconductor device includes an oxide semiconductor, a first transistor, a second transistor, and a dummy word line. A channel formation region in the first transistor and a channel formation region in the second transistor are formed in different regions in the oxide semiconductor. The dummy word line is provided to extend between the channel formation region in the first transistor and the channel formation region in the second transistor. By applying a predetermined potential to the dummy word line, the first transistor and the second transistor are electrically isolated in a region of the oxide semiconductor which intersects the dummy word line.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: September 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Tatsunori Inoue
  • Publication number: 20190221896
    Abstract: A semiconductor device in which a circuit and a battery are efficiently stored is provided. In the semiconductor device, a first transistor, a second transistor, and a secondary battery are provided over one substrate. A channel region of the second transistor includes an oxide semiconductor. The secondary battery includes a solid electrolyte, and can be fabricated by a semiconductor manufacturing process. The substrate may be a semiconductor substrate or a flexible substrate. The secondary battery has a function of being wirelessly charged.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventors: Junpei MOMO, Kazutaka KURIKI, Hiromichi GODO, Shunpei YAMAZAKI
  • Publication number: 20190157262
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 23, 2019
    Inventors: Junpei MOMO, Kazutaka KURIKI, Hiromichi GODO
  • Patent number: 10296157
    Abstract: To provide a display device which includes a touch sensor and a large number of pixels and in which a driver circuit of a display portion and a driver circuit of a touch sensor are formed in one IC. The display device includes the display portion, the touch sensor, and a plurality of ICs. The plurality of ICs each include a first circuit. One of the plurality of ICs includes a second circuit and a third circuit. The first circuit has a function of outputting a video signal to the display portion. The second circuit has a function of outputting a signal for driving a sensor element included in the touch sensor. The third circuit has a function of converting an analog signal output from the sensor element into a digital signal.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 21, 2019
    Inventors: Kei Takahashi, Wataru Uesugi, Hiromichi Godo
  • Patent number: 10290908
    Abstract: A semiconductor device in which a circuit and a battery are efficiently stored is provided. In the semiconductor device, a first transistor, a second transistor, and a secondary battery are provided over one substrate. A channel region of the second transistor includes an oxide semiconductor. The secondary battery includes a solid electrolyte, and can be fabricated by a semiconductor manufacturing process. The substrate may be a semiconductor substrate or a flexible substrate. The secondary battery has a function of being wirelessly charged.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo, Shunpei Yamazaki
  • Patent number: 10290720
    Abstract: The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Hiroshi Fujiki, Hiromichi Godo, Yasumasa Yamane
  • Patent number: 10270056
    Abstract: A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hiromichi Godo, Kaoru Tsuchiya
  • Patent number: 10204898
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo
  • Publication number: 20180323306
    Abstract: To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced.
    Type: Application
    Filed: July 18, 2018
    Publication date: November 8, 2018
    Inventors: Hiromichi GODO, Tetsuhiro TANAKA
  • Patent number: 10084072
    Abstract: A semiconductor device in which a shift of the threshold voltage of a transistor is suppressed is provided. A semiconductor device in which a decrease in the on-state current of a transistor is suppressed is provided. The semiconductor device is manufactured as follows: forming a gate electrode layer over a substrate; forming a gate insulating film over the gate electrode layer; forming an oxide semiconductor film over the gate insulating film; forming a metal oxide film having a higher reducing property than the oxide semiconductor film over the oxide semiconductor film; performing heat treatment while the metal oxide film and the oxide semiconductor film are in contact with each other, thereby the metal oxide film is reduced so that a metal film is formed; and processing the metal film to form a source electrode layer and a drain electrode layer.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiromichi Godo
  • Patent number: 9997638
    Abstract: An object is to reduce to reduce variation in threshold voltage to stabilize electric characteristics of thin film transistors each using an oxide semiconductor layer. An object is to reduce an off current. The thin film transistor using an oxide semiconductor layer is formed by stacking an oxide semiconductor layer containing insulating oxide over the oxide semiconductor layer so that the oxide semiconductor layer and source and drain electrode layers are in contact with each other with the oxide semiconductor layer containing insulating oxide interposed therebetween; whereby, variation in threshold voltage of the thin film transistors can be reduced and thus the electric characteristics can be stabilized. Further, an off current can be reduced.
    Type: Grant
    Filed: May 18, 2017
    Date of Patent: June 12, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Kengo Akimoto, Shunpei Yamazaki
  • Publication number: 20180090710
    Abstract: A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided.
    Type: Application
    Filed: September 25, 2017
    Publication date: March 29, 2018
    Applicant: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hiromichi Godo, Kaoru Tsuchiya
  • Patent number: 9887297
    Abstract: A semiconductor device includes a gate electrode having higher Gibbs free energy for oxidation than a gate insulating film. An oxide semiconductor layer having a fin shape is formed over an insulating surface, a gate insulating film is formed over the oxide semiconductor layer, a gate electrode including an oxide layer and facing top and side surfaces of the oxide semiconductor layer with the gate insulating film located therebetween is formed, and then by performing heat treatment, a gate electrode is reduced and oxygen is supplied to the oxide semiconductor layer through the gate insulating film.
    Type: Grant
    Filed: September 12, 2014
    Date of Patent: February 6, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Tetsuhiro Tanaka, Hiromichi Godo
  • Patent number: 9859443
    Abstract: Provided is a field-effect transistor (FET) having small off-state current, which is used in a miniaturized semiconductor integrated circuit. The field-effect transistor includes a thin oxide semiconductor which is formed substantially perpendicular to an insulating surface, a gate insulating film formed to cover the oxide semiconductor, and a gate electrode which is formed to cover the gate insulating film. The gate electrode partly overlaps a source electrode and a drain electrode. The source electrode and the drain electrode are in contact with at least a top surface of the oxide semiconductor. In this structure, three surfaces of the thin oxide semiconductor are covered with the gate electrode, so that electrons injected from the source electrode or the drain electrode can be effectively removed, and most of the space between the source electrode and the drain electrode can be a depletion region; thus, off-state current can be reduced.
    Type: Grant
    Filed: November 29, 2016
    Date of Patent: January 2, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Yasuhiko Takemura
  • Publication number: 20170373193
    Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
    Type: Application
    Filed: June 16, 2017
    Publication date: December 28, 2017
    Inventors: Shunpei YAMAZAKI, Hiromichi GODO, Satoshi KOBAYASHI
  • Patent number: 9852108
    Abstract: Disclosed is a semiconductor device including an insulating layer, a source electrode and a drain electrode embedded in the insulating layer, an oxide semiconductor layer in contact with the insulating layer, the source electrode, and the drain electrode, a gate insulating layer covering the oxide semiconductor layer, and a gate electrode over the gate insulating layer. The upper surface of the surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less. There is a difference in height between an upper surface of the insulating layer and each of an upper surface of the source electrode and an upper surface of the drain electrode. The difference in height is preferably 5 nm or more. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.
    Type: Grant
    Filed: March 24, 2016
    Date of Patent: December 26, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo
  • Publication number: 20170309721
    Abstract: The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced.
    Type: Application
    Filed: July 6, 2017
    Publication date: October 26, 2017
    Inventors: Shunpei YAMAZAKI, Hideomi SUZAWA, Hiroshi FUJIKI, Hiromichi GODO, Yasumasa YAMANE
  • Patent number: 9799773
    Abstract: A transistor which withstands a high voltage and controls large electric power can be provided. A transistor is provided which includes a gate electrode, a gate insulating layer over the gate electrode, an oxide semiconductor layer which is over the gate insulating layer and overlaps with the gate electrode, and a source electrode and a drain electrode which are in contact with the oxide semiconductor layer and whose end portions overlap with the gate electrode. The gate insulating layer includes a first region overlapping with the end portion of the drain electrode and a second region adjacent to the first region. The first region has smaller capacitance than the second region.
    Type: Grant
    Filed: January 26, 2012
    Date of Patent: October 24, 2017
    Assignee: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
    Inventors: Hiromichi Godo, Satoshi Kobayashi, Masashi Tsubuku
  • Patent number: 9780329
    Abstract: A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided.
    Type: Grant
    Filed: November 23, 2016
    Date of Patent: October 3, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hiromichi Godo, Kaoru Tsuchiya
  • Patent number: 9761588
    Abstract: A conventional DRAM needs to be refreshed at an interval of several tens of milliseconds to hold data, which results in large power consumption. In addition, a transistor therein is frequently turned on and off; thus, deterioration of the transistor is also a problem. These problems become significant as the memory capacity increases and transistor miniaturization advances. A transistor is provided which includes a wide-gap semiconductor and has a trench structure including a trench for a gate electrode and a trench for element isolation. Even when the distance between a source electrode and a drain electrode is decreased, the occurrence of a short-channel effect can be suppressed by setting the depth of the trench for the gate electrode as appropriate.
    Type: Grant
    Filed: October 26, 2015
    Date of Patent: September 12, 2017
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo