Patents by Inventor Hiromichi Godo

Hiromichi Godo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10910499
    Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
    Type: Grant
    Filed: February 6, 2020
    Date of Patent: February 2, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Satoshi Kobayashi
  • Patent number: 10903206
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: January 26, 2021
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo
  • Publication number: 20210005755
    Abstract: It is an object to provide a highly reliable thin film transistor with stable electric characteristics, which includes an oxide semiconductor film. The channel length of the thin film transistor including the oxide semiconductor film is in the range of 1.5 ?m to 100 ?m inclusive, preferably 3 ?m to 10 ?m inclusive; when the amount of change in threshold voltage is less than or equal to 3 V, preferably less than or equal to 1.5 V in an operation temperature range of room temperature to 180° C. inclusive or ?25° C. to 150° C. inclusive, a semiconductor device with stable electric characteristics can be manufactured. In particular, in a display device which is an embodiment of the semiconductor device, display unevenness due to variation in threshold voltage can be reduced.
    Type: Application
    Filed: September 21, 2020
    Publication date: January 7, 2021
    Inventors: Shunpei YAMAZAKI, Masashi TSUBUKU, Hiromichi GODO
  • Publication number: 20200411917
    Abstract: A semiconductor device in which a circuit and a battery are efficiently stored is provided. In the semiconductor device, a first transistor, a second transistor, and a secondary battery are provided over one substrate. A channel region of the second transistor includes an oxide semiconductor. The secondary battery includes a solid electrolyte, and can be fabricated by a semiconductor manufacturing process. The substrate may be a semiconductor substrate or a flexible substrate. The secondary battery has a function of being wirelessly charged.
    Type: Application
    Filed: September 14, 2020
    Publication date: December 31, 2020
    Inventors: Junpei MOMO, Kazutaka KURIKI, Hiromichi GODO, Shunpei YAMAZAKI
  • Publication number: 20200402977
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Application
    Filed: September 2, 2020
    Publication date: December 24, 2020
    Inventors: Junpei MOMO, Kazutaka KURIKI, Hiromichi GODO
  • Patent number: 10862177
    Abstract: A semiconductor device in which a circuit and a battery are efficiently stored is provided. In the semiconductor device, a first transistor, a second transistor, and a secondary battery are provided over one substrate. A channel region of the second transistor includes an oxide semiconductor. The secondary battery includes a solid electrolyte, and can be fabricated by a semiconductor manufacturing process. The substrate may be a semiconductor substrate or a flexible substrate. The secondary battery has a function of being wirelessly charged.
    Type: Grant
    Filed: March 21, 2019
    Date of Patent: December 8, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo, Shunpei Yamazaki
  • Patent number: 10749033
    Abstract: Disclosed is a semiconductor device including: an insulating layer; a source electrode and a drain electrode embedded in the insulating layer; an oxide semiconductor layer in contact and over the insulating layer, the source electrode, and the drain electrode; a gate insulating layer over and covering the oxide semiconductor layer; and a gate electrode over the gate insulating layer, where the upper surfaces of the insulating layer, the source electrode, and the drain electrode exist coplanarly. The upper surface of the insulating layer, which is in contact with the oxide semiconductor layer, has a root-mean-square (RMS) roughness of 1 nm or less, and the difference in height between the upper surface of the insulating layer and the upper surface of the source electrode or the drain electrode is less than 5 nm. This structure contributes to the suppression of defects of the semiconductor device and enables their miniaturization.
    Type: Grant
    Filed: February 4, 2014
    Date of Patent: August 18, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Ryota Imahayashi, Kiyoshi Kato
  • Publication number: 20200176607
    Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
    Type: Application
    Filed: February 6, 2020
    Publication date: June 4, 2020
    Inventors: Shunpei YAMAZAKI, Hiromichi GODO, Satoshi KOBAYASHI
  • Patent number: 10615283
    Abstract: An object is to provide a semiconductor device having electrical characteristics such as high withstand voltage, low reverse saturation current, and high on-state current. In particular, an object is to provide a power diode and a rectifier which include non-linear elements. An embodiment of the present invention is a semiconductor device including a first electrode, a gate insulating layer covering the first electrode, an oxide semiconductor layer in contact with the gate insulating layer and overlapping with the first electrode, a pair of second electrodes covering end portions of the oxide semiconductor layer, an insulating layer covering the pair of second electrodes and the oxide semiconductor layer, and a third electrode in contact with the insulating layer and between the pair of second electrodes. The pair of second electrodes are in contact with end surfaces of the oxide semiconductor layer.
    Type: Grant
    Filed: June 16, 2017
    Date of Patent: April 7, 2020
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hiromichi Godo, Satoshi Kobayashi
  • Publication number: 20200051211
    Abstract: An image processing method that generates high-resolution image data from low-resolution image data and an image receiving apparatus that is operated by the image processing method are provided. In the image processing method that generates high-resolution image data from low-resolution image data, the low-resolution image data is divided to generate a plurality of first image data, among the plurality of first image data, one of two adjacent image data is second image data, and the other is third image data. Surroundings of the second image data are supplemented with pixel data to generate fourth image data. The pixel data includes part of the third image data. A convolutional neural network using the fourth image data as an input is implemented, fifth image data is output from the convolutional neural network, and a plurality of the fifth image data is combined to generate high-resolution image data. The image receiving apparatus is operated by the image processing method.
    Type: Application
    Filed: April 9, 2018
    Publication date: February 13, 2020
    Inventors: Masataka SHIOKAWA, Kei TAKAHASHI, Yuji IWAKI, Hiromichi GODO
  • Patent number: 10411013
    Abstract: To provide a semiconductor device with large storage capacity and low power consumption. The semiconductor device includes an oxide semiconductor, a first transistor, a second transistor, and a dummy word line. A channel formation region in the first transistor and a channel formation region in the second transistor are formed in different regions in the oxide semiconductor. The dummy word line is provided to extend between the channel formation region in the first transistor and the channel formation region in the second transistor. By applying a predetermined potential to the dummy word line, the first transistor and the second transistor are electrically isolated in a region of the oxide semiconductor which intersects the dummy word line.
    Type: Grant
    Filed: January 17, 2017
    Date of Patent: September 10, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Hiromichi Godo, Tatsunori Inoue
  • Publication number: 20190221896
    Abstract: A semiconductor device in which a circuit and a battery are efficiently stored is provided. In the semiconductor device, a first transistor, a second transistor, and a secondary battery are provided over one substrate. A channel region of the second transistor includes an oxide semiconductor. The secondary battery includes a solid electrolyte, and can be fabricated by a semiconductor manufacturing process. The substrate may be a semiconductor substrate or a flexible substrate. The secondary battery has a function of being wirelessly charged.
    Type: Application
    Filed: March 21, 2019
    Publication date: July 18, 2019
    Inventors: Junpei MOMO, Kazutaka KURIKI, Hiromichi GODO, Shunpei YAMAZAKI
  • Publication number: 20190157262
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Application
    Filed: January 3, 2019
    Publication date: May 23, 2019
    Inventors: Junpei MOMO, Kazutaka KURIKI, Hiromichi GODO
  • Patent number: 10296157
    Abstract: To provide a display device which includes a touch sensor and a large number of pixels and in which a driver circuit of a display portion and a driver circuit of a touch sensor are formed in one IC. The display device includes the display portion, the touch sensor, and a plurality of ICs. The plurality of ICs each include a first circuit. One of the plurality of ICs includes a second circuit and a third circuit. The first circuit has a function of outputting a video signal to the display portion. The second circuit has a function of outputting a signal for driving a sensor element included in the touch sensor. The third circuit has a function of converting an analog signal output from the sensor element into a digital signal.
    Type: Grant
    Filed: May 23, 2016
    Date of Patent: May 21, 2019
    Inventors: Kei Takahashi, Wataru Uesugi, Hiromichi Godo
  • Patent number: 10290720
    Abstract: The reliability of a semiconductor device is increased by suppression of a variation in electric characteristics of a transistor as much as possible. As a cause of a variation in electric characteristics of a transistor including an oxide semiconductor, the concentration of hydrogen in the oxide semiconductor, the density of oxygen vacancies in the oxide semiconductor, or the like can be given. A source electrode and a drain electrode are formed using a conductive material which is easily bonded to oxygen. A channel formation region is formed using an oxide layer formed by a sputtering method or the like under an atmosphere containing oxygen. Thus, the concentration of hydrogen in a stack, in particular, the concentration of hydrogen in a channel formation region can be reduced.
    Type: Grant
    Filed: July 6, 2017
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Shunpei Yamazaki, Hideomi Suzawa, Hiroshi Fujiki, Hiromichi Godo, Yasumasa Yamane
  • Patent number: 10290908
    Abstract: A semiconductor device in which a circuit and a battery are efficiently stored is provided. In the semiconductor device, a first transistor, a second transistor, and a secondary battery are provided over one substrate. A channel region of the second transistor includes an oxide semiconductor. The secondary battery includes a solid electrolyte, and can be fabricated by a semiconductor manufacturing process. The substrate may be a semiconductor substrate or a flexible substrate. The secondary battery has a function of being wirelessly charged.
    Type: Grant
    Filed: February 2, 2015
    Date of Patent: May 14, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo, Shunpei Yamazaki
  • Patent number: 10270056
    Abstract: A novel display device with higher reliability having a structure of blocking moisture and oxygen, which deteriorate the characteristics of the display device, from penetrating through a sealing region and a method of manufacturing thereof is provided.
    Type: Grant
    Filed: September 25, 2017
    Date of Patent: April 23, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Masayuki Sakakura, Hiromichi Godo, Kaoru Tsuchiya
  • Patent number: 10204898
    Abstract: A semiconductor device in which a circuit and a power storage element are efficiently placed is provided. The semiconductor device includes a first transistor, a second transistor, and an electric double-layer capacitor. The first transistor, the second transistor, and the electric double-layer capacitor are provided over one substrate. A band gap of a semiconductor constituting a channel region of the second transistor is wider than a band gap of a semiconductor constituting a channel region of the first transistor. The electric double-layer capacitor includes a solid electrolyte.
    Type: Grant
    Filed: August 4, 2015
    Date of Patent: February 12, 2019
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventors: Junpei Momo, Kazutaka Kuriki, Hiromichi Godo
  • Publication number: 20180323306
    Abstract: To reduce oxygen vacancies in an oxide semiconductor film and the vicinity of the oxide semiconductor film and to improve electric characteristics of a transistor including the oxide semiconductor film. A semiconductor device includes a gate electrode whose Gibbs free energy for oxidation is higher than that of a gate insulating film. In a region where the gate electrode is in contact with the gate insulating film, oxygen moves from the gate electrode to the gate insulating film, which is caused because the gate electrode has higher Gibbs free energy for oxidation than the gate insulating film. The oxygen passes through the gate insulating film and is supplied to the oxide semiconductor film in contact with the gate insulating film, whereby oxygen vacancies in the oxide semiconductor film and the vicinity of the oxide semiconductor film can be reduced.
    Type: Application
    Filed: July 18, 2018
    Publication date: November 8, 2018
    Inventors: Hiromichi GODO, Tetsuhiro TANAKA
  • Patent number: 10084072
    Abstract: A semiconductor device in which a shift of the threshold voltage of a transistor is suppressed is provided. A semiconductor device in which a decrease in the on-state current of a transistor is suppressed is provided. The semiconductor device is manufactured as follows: forming a gate electrode layer over a substrate; forming a gate insulating film over the gate electrode layer; forming an oxide semiconductor film over the gate insulating film; forming a metal oxide film having a higher reducing property than the oxide semiconductor film over the oxide semiconductor film; performing heat treatment while the metal oxide film and the oxide semiconductor film are in contact with each other, thereby the metal oxide film is reduced so that a metal film is formed; and processing the metal film to form a source electrode layer and a drain electrode layer.
    Type: Grant
    Filed: March 20, 2017
    Date of Patent: September 25, 2018
    Assignee: Semiconductor Energy Laboratory Co., Ltd.
    Inventor: Hiromichi Godo