Patents by Inventor Hiromichi Makishima
Hiromichi Makishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 9893832Abstract: An Add Drop Multiplexer (ADM) includes a separating unit that extracts, from an ODU4 storing therein a plurality of HO-ODUs each of which stores therein at least one LO-ODU, first MSI values which correspond to the HO-ODUs and each of which identifies a different one of the LO-ODUs for each LO-ODU. The ADM includes a converting unit that converts the first MSI values which correspond to the HO-ODUs and each of which identifies a different one of the LO-ODUs, into second MSI values which correspond to the ODU4 and each of which identifies a different one of the LO-ODUs. The ADM includes an ODU processing unit that extracts the LO-ODUs from the ODU4, on the basis of the second MSI values resulting from the conversion by the converting unit.Type: GrantFiled: December 16, 2014Date of Patent: February 13, 2018Assignee: FUJITSU LIMITEDInventors: Hidetaka Kawahara, Hiromichi Makishima
-
Patent number: 9819432Abstract: A transmission apparatus includes: a generator configured to generate position information indicating a position of header information of each of a plurality of first signals from a second signal nesting the plurality of first signals; a storage configured to store the position information generated by the generator and the plurality of first signals; a monitor configured to read the position information and the plurality of first signals stored in the storage, and to monitor the header information of each of the plurality of first signals based on the position information; and an output unit configured to output the plurality of first signals after monitoring the contents of the header information.Type: GrantFiled: April 8, 2016Date of Patent: November 14, 2017Assignee: FUJITSU LIMITEDInventors: Hiromichi Makishima, Hidetaka Kawahara, Shingo Hotta, Hiroyuki Kitajima
-
Patent number: 9735907Abstract: A transmission device to multiplex in a first signal a plurality of second signals each having a low rate as compared with the first signal, the transmission device includes: a plurality of memories to store the plurality of second signals; a selector to select one of the second signals read from the plurality of memories; and a controller to control read timing to read the plurality of second signals from the plurality of memories and signal selection timing to select the one of the second signals by the selector so as to execute rearrangement processing of the plurality of second signals read from the plurality of memories in accordance with cross-connect setting information for the plurality of second signals and shift processing of the plurality of second signals read from the plurality of memories in accordance with multiplexing positions of the plurality of second signals for the first signal.Type: GrantFiled: October 22, 2015Date of Patent: August 15, 2017Assignee: FUJITSU LIMITEDInventors: Hiromichi Makishima, Hidetaka Kawahara, Yuji Obana, Kazumasa Mikami, Wataru Odashima, Shingo Hotta, Hiroyuki Kitajima
-
Patent number: 9647781Abstract: A data reception device which receives data transmitted through a plurality of transmission lines. The data reception device includes a position detection unit which corrects a skew of data transmitted respectively through the plurality of transmission lines, and detects for each lane a position of a marker for identification of a lane which is assigned the data, and an information extraction unit which extracts identification information indicated by the marker for each lane using a result of the detection of the position of the marker by the position detection unit.Type: GrantFiled: October 17, 2013Date of Patent: May 9, 2017Assignee: FUJITSU LIMITEDInventors: Katsutoshi Miyaji, Hiroyuki Homma, Ken Shiine, Hiromichi Makishima
-
Publication number: 20170048098Abstract: A receiving apparatus includes: a memory configured to store information including priority ranks for accessing pieces of warning information; and a controller configured to extract the pieces of warning information from signals having different transmission rate, access, in descending order of the priority ranks, the pieces of warning information stored in a storage, and execute a transfer process.Type: ApplicationFiled: May 18, 2016Publication date: February 16, 2017Applicant: FUJITSU LIMITEDInventors: HIDETAKA KAWAHARA, Hiromichi Makishima
-
Publication number: 20160337033Abstract: A transmission apparatus includes: a generator configured to generate position information indicating a position of header information of each of a plurality of first signals from a second signal nesting the plurality of first signals; a storage configured to store the position information generated by the generator and the plurality of first signals; a monitor configured to read the position information and the plurality of first signals stored in the storage, and to monitor the header information of each of the plurality of first signals based on the position information; and an output unit configured to output the plurality of first signals after monitoring the contents of the header information.Type: ApplicationFiled: April 8, 2016Publication date: November 17, 2016Applicant: FUJITSU LIMITEDInventors: Hiromichi Makishima, Hidetaka Kawahara, Shingo Hotta, Hiroyuki Kitajima
-
Publication number: 20160142799Abstract: A transmission device to multiplex in a first signal a plurality of second signals each having a low rate as compared with the first signal, the transmission device includes: a plurality of memories to store the plurality of second signals; a selector to select one of the second signals read from the plurality of memories; and a controller to control read timing to read the plurality of second signals from the plurality of memories and signal selection timing to select the one of the second signals by the selector so as to execute rearrangement processing of the plurality of second signals read from the plurality of memories in accordance with cross-connect setting information for the plurality of second signals and shift processing of the plurality of second signals read from the plurality of memories in accordance with multiplexing positions of the plurality of second signals for the first signal.Type: ApplicationFiled: October 22, 2015Publication date: May 19, 2016Applicant: FUJITSU LIMITEDInventors: Hiromichi MAKISHIMA, Hidetaka KAWAHARA, Yuji OBANA, Kazumasa MIKAMI, Wataru ODASHIMA, Shingo HOTTA, Hiroyuki KITAJIMA
-
Publication number: 20160142798Abstract: A transmission apparatus includes: a reception processing unit configured to perform a reception processing on a first signal into which second signals having different rates and including overhead information are hierarchically multiplexed; and a common overhead processing unit configured to process the overhead information included in the first and second signals according to a common rate to hierarchical layers.Type: ApplicationFiled: October 21, 2015Publication date: May 19, 2016Applicant: FUJITSU LIMITEDInventors: HIDETAKA KAWAHARA, Hiromichi Makishima, Hiroyuki Kitajima, Yuji OBANA, Shingo HOTTA, Wataru Odashima
-
Publication number: 20150207584Abstract: An Add Drop Multiplexer (ADM) includes a separating unit that extracts, from an ODU4 storing therein a plurality of HO-ODUs each of which stores therein at least one LO-ODU, first MSI values which correspond to the HO-ODUs and each of which identifies a different one of the LO-ODUs for each LO-ODU. The ADM includes a converting unit that converts the first MSI values which correspond to the HO-ODUs and each of which identifies a different one of the LO-ODUs, into second MSI values which correspond to the ODU4 and each of which identifies a different one of the LO-ODUs. The ADM includes an ODU processing unit that extracts the LO-ODUs from the ODU4, on the basis of the second MSI values resulting from the conversion by the converting unit.Type: ApplicationFiled: December 16, 2014Publication date: July 23, 2015Inventors: HIDETAKA KAWAHARA, Hiromichi Makishima
-
Patent number: 8767748Abstract: A signal distribution circuit includes: first to n-th input lines on which first to n-th signals are respectively input; first to (n?1)th selectors each of which selects one of two inputs under the control of a select signal; and a first output line on which the first signal is output and second to n-th output lines on which output signals of the first to (n?1)th selectors are respectively output, wherein: the first and second inputs of the first selector are supplied with the first signal and the second signal, respectively, the first and second inputs of the i-th selector (i is an integer between 2 and (n?1)) are supplied with the output signal of the (i?1)th selector and the (i+1)th signal, respectively, and any of the selectors, when selected by the select signal, selects the second input and, when not selected by the select signal, selects the first input.Type: GrantFiled: August 29, 2011Date of Patent: July 1, 2014Assignee: Fujitsu LimitedInventors: Masafumi Ohta, Hiromichi Makishima, Hiroyuki Honma
-
Publication number: 20140044137Abstract: A data reception device which receives data transmitted through a plurality of transmission lines. The data reception device includes a position detection unit which corrects a skew of data transmitted respectively through the plurality of transmission lines, and detects for each lane a position of a marker for identification of a lane which is assigned the data, and an information extraction unit which extracts identification information indicated by the marker for each lane using a result of the detection of the position of the marker by the position detection unit.Type: ApplicationFiled: October 17, 2013Publication date: February 13, 2014Applicant: FUJITSU LIMITEDInventors: KATSUTOSHI MIYAJI, HIROYUKI HOMMA, Ken SHIINE, Hiromichi MAKISHIMA
-
Patent number: 8571073Abstract: An apparatus for mapping multiple lower-speed signal transmission frames to a higher-speed signal transmission frame. The apparatus includes buffers configured to buffer the lower-speed signal transmission frames, determination units configured to determine frequency justification information for the lower-speed signal transmission frames, a barrel shifter configured to receive signals output from the buffers, and a controller configured to control the barrel shifter to map the lower-speed signal transmission frames to the higher-speed signal transmission frame based on external settings for the respective lower-speed signal transmission frames and the frequency justification information determined by the determination units. When the minimum unit of the lower-speed signal transmission frames is a channel, the number of the buffers and the number of the determination units correspond to the maximum number of channels that can be multiplexed in the higher-speed signal transmission frame.Type: GrantFiled: February 3, 2012Date of Patent: October 29, 2013Assignee: Fujitsu LimitedInventors: Toshiaki Ohkubo, Toru Katagiri, Hiroyuki Honma, Hiromichi Makishima, Hiroyuki Kitajima
-
Patent number: 8521176Abstract: In a transmission apparatus, a comparison unit provides threshold values associated with an amount of data indicating a signal frequency, and compares an input parameter obtained by cumulatively adding a correction amount to the parameter with the threshold values. When the input parameter is within a range defined by the threshold values, a correction unit outputs a value of the input parameter. When the input parameter is out of the defined range, the correction unit outputs an associated one of the threshold values so as to eliminate an amount exceeding or falling short of the defined range, to thereby correct the input parameter. An addition unit detects the correction amount which is an amount of the immediately preceding value of the input parameter exceeding or falling short of the defined range, and cumulatively adds the correction amount to the input parameter used for the comparison of this time.Type: GrantFiled: March 30, 2012Date of Patent: August 27, 2013Assignee: Fujitsu LimitedInventors: Shingo Hotta, Hiromichi Makishima, Hiroyuki Honma, Ichirou Yokokura
-
Publication number: 20130058643Abstract: A data amount derivation apparatus includes: a first calculator configured to derive, for one series of parallelized mapping signals, amount of data in each frame period for a frame into which the parallelized mapping signals are mapped; and a second calculator configured to sum up amounts of data in N frame periods, where N is an integer, and to derive the resulting summation value as the amount of data to be mapped into the frame, each of the amounts of data in each of the frame periods being derived by the first calculator.Type: ApplicationFiled: October 31, 2012Publication date: March 7, 2013Applicant: FUJITSU LIMITEDInventors: Hiroyuki HONMA, Toru Katagiri, Hiromichi Makishima, Masahiro Shioda, Hiroyuki Kitajima, Ichiro Yokokura
-
Publication number: 20120302185Abstract: In a transmission apparatus, a comparison unit provides threshold values associated with an amount of data indicating a signal frequency, and compares an input parameter obtained by cumulatively adding a correction amount to the parameter with the threshold values. When the input parameter is within a range defined by the threshold values, a correction unit outputs a value of the input parameter. When the input parameter is out of the defined range, the correction unit outputs an associated one of the threshold values so as to eliminate an amount exceeding or falling short of the defined range, to thereby correct the input parameter. An addition unit detects the correction amount which is an amount of the immediately preceding value of the input parameter exceeding or falling short of the defined range, and cumulatively adds the correction amount to the input parameter used for the comparison of this time.Type: ApplicationFiled: March 30, 2012Publication date: November 29, 2012Applicant: FUJITSU LIMITEDInventors: Shingo HOTTA, Hiromichi MAKISHIMA, Hiroyuki HONMA, Ichirou YOKOKURA
-
Patent number: 8300660Abstract: A transmitting apparatus includes a detecting unit that detects deviation and balance relative to a specified bit rate of a frame signal input at a constant bit rate; a dividing unit that reads at constant intervals from a buffer storing the frame signal and outputs a signal divided into a plurality of segments having a predetermined data length; and a correcting unit that, based on the deviation and balance detected by the detecting unit, corrects the data length for the division by the dividing unit.Type: GrantFiled: January 30, 2010Date of Patent: October 30, 2012Assignee: Fujitsu LimitedInventors: Ichiro Yokokura, Hiromichi Makishima, Shinji Sawane
-
Publication number: 20120251127Abstract: An apparatus for mapping multiple lower-speed signal transmission frames to a higher-speed signal transmission frame. The apparatus includes buffers configured to buffer the lower-speed signal transmission frames, determination units configured to determine frequency justification information for the lower-speed signal transmission frames, a barrel shifter configured to receive signals output from the buffers, and a controller configured to control the barrel shifter to map the lower-speed signal transmission frames to the higher-speed signal transmission frame based on external settings for the respective lower-speed signal transmission frames and the frequency justification information determined by the determination units. When the minimum unit of the lower-speed signal transmission frames is a channel, the number of the buffers and the number of the determination units correspond to the maximum number of channels that can be multiplexed in the higher-speed signal transmission frame.Type: ApplicationFiled: February 3, 2012Publication date: October 4, 2012Applicant: FUJITSU LIMITEDInventors: Toshiaki OHKUBO, Toru Katagiri, Hiroyuki Honma, Hiromichi Makishima, Hiroyuki Kitajima
-
Publication number: 20120134367Abstract: A signal distribution circuit includes: first to n-th input lines on which first to n-th signals are respectively input; first to (n?1)th selectors each of which selects one of two inputs under the control of a select signal; and a first output line on which the first signal is output and second to n-th output lines on which output signals of the first to (n?1)th selectors are respectively output, wherein: the first and second inputs of the first selector are supplied with the first signal and the second signal, respectively, the first and second inputs of the i-th selector (i is an integer between 2 and (n?1)) are supplied with the output signal of the (i?1)th selector and the (i+1)th signal, respectively, and any of the selectors, when selected by the select signal, selects the second input and, when not selected by the select signal, selects the first input.Type: ApplicationFiled: August 29, 2011Publication date: May 31, 2012Applicant: FUJITSU LIMITEDInventors: Masafumi OHTA, Hiromichi MAKISHIMA, Hiroyuki HONMA
-
Publication number: 20100238954Abstract: A transmitting apparatus includes a detecting unit that detects deviation and balance relative to a specified bit rate of a frame signal input at a constant bit rate; a dividing unit that reads at constant intervals from a buffer storing the frame signal and outputs a signal divided into a plurality of segments having a predetermined data length; and a correcting unit that, based on the deviation and balance detected by the detecting unit, corrects the data length for the division by the dividing unit.Type: ApplicationFiled: January 30, 2010Publication date: September 23, 2010Applicant: FUJITSU LIMITEDInventors: Ichiro YOKOKURA, Hiromichi Makishima, Shinji Sawane
-
Patent number: 7467362Abstract: A failure detection improvement apparatus that modifies a net list comprises; a net list input section to which the net list is input; a circuit modification section that adds an observation FF to an appropriate location on the net list; and a net list output section that outputs the net list that has been modified by the circuit modification section.Type: GrantFiled: June 28, 2005Date of Patent: December 16, 2008Assignee: Fujitsu LimitedInventors: Seiji Shigihara, Hiromichi Makishima, Yasutomo Honma