Patents by Inventor Hiromichi Makishima

Hiromichi Makishima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070143726
    Abstract: There is provided a circuit design apparatus that performs logic design for realizing a reduction of power consumption and circuit simplification. A circuit design apparatus interprets RTL of a design target to perform structure analysis thereof (S2), estimates generation of a clock gating based on a result of the structure analysis, detects RTL description of an EN generation logic (S3), and detects the same EN generation logic (S4). The apparatus determines an insertion location of the clock gating circuit and reorganization of logical hierarchies based on the detected EN generation logic (S5), instructs logical hierarchy reorganization to be performed in logic synthesis (S8) and performs design change processing (S6). The apparatus performs logic synthesis based on RTL after design change and instruction of logical hierarchy reorganization (S10), and layouts a concrete circuit configuration (S12).
    Type: Application
    Filed: March 21, 2006
    Publication date: June 21, 2007
    Applicant: Fujitsu Limited
    Inventors: Ryo Mizutani, Seiji Shigihara, Hiromichi Makishima, Yasutomo Honma
  • Publication number: 20060236154
    Abstract: A failure detection improvement apparatus that modifies a net list comprises; a net list input section to which the net list is input; a circuit modification section that adds an observation FF to an appropriate location on the net list; and a net list output section that outputs the net list that has been modified by the circuit modification section.
    Type: Application
    Filed: June 28, 2005
    Publication date: October 19, 2006
    Applicant: FUJITSU LIMITED
    Inventors: Seiji Shigihara, Hiromichi Makishima, Yasutomo Honma
  • Patent number: 6788684
    Abstract: An ATM cell bridge apparatus and a cell bridging method as well as an information transmission system having a cell bridge apparatus by which a cell can be outputted in accordance with a priority degree even during multicast processing. The ATM cell bridge apparatus includes a buffer unit for storing cell data of input cells, a buffer control unit for controlling writing and reading out of the cell data into and from the buffer unit, a cell production control unit for managing multicast information of the cell data read out from the buffer unit by the buffer control unit and producing a cell to be outputted from header information of the cell data, and a cell outputting unit for outputting the cell produced by the cell production control unit and issuing a cell data readout request to the buffer control unit.
    Type: Grant
    Filed: November 30, 1998
    Date of Patent: September 7, 2004
    Assignee: Fujitsu Limited
    Inventors: Hiromichi Makishima, Yuji Obana, Hiroyuki Asano, Toshiaki Ookubo, Hideo Abe
  • Publication number: 20030133453
    Abstract: The invention provides an ATM cell bridge apparatus and a cell bridging method as well as an information transmission system having a cell bridge apparatus by which a cell can be outputted in accordance with a priority degree of it even during multicast processing and the burden to a transmission source is moderated by intra-port multicast on an ATM transmission apparatus and besides the transmission efficiency of cells having high priority degrees is raised.
    Type: Application
    Filed: November 30, 1998
    Publication date: July 17, 2003
    Inventors: HIROMICHI MAKISHIMA, YUJI OBANA, HIROYUKI ASANO, TOSHIAKI OOKUBO, HIDEO ABE