Patents by Inventor Hiromichi Ohashi

Hiromichi Ohashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7244974
    Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semi-conductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.
    Type: Grant
    Filed: July 28, 2005
    Date of Patent: July 17, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Ichiro Omura, Hiromichi Ohashi
  • Patent number: 7238576
    Abstract: A semiconductor device comprises a drain layer of first conductivity type, drift layers of first and second conductivity types on the drain layer, an insulating film between the drift layers and contacting the drift layers, a first base layer of second conductivity type on a surface of the drift layer of first conductivity type, a source layer of first conductivity type selectively provided on a surface of the first base layer of second conductivity type, a gate insulating film on the first base layer of second conductivity type between the source layer and the drift layer, a gate electrode on the gate insulating film, a second base layer of second conductivity type on a surface of the drift layer, a first main electrode on the drain layer, and a second main electrode on the source layer, the first base layer and the second base layer.
    Type: Grant
    Filed: April 1, 2003
    Date of Patent: July 3, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Masakazu Yamaguchi, Ichiro Omura, Wataru Saito, Takashi Shinohe, Hiromichi Ohashi
  • Patent number: 7102179
    Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semiconductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.
    Type: Grant
    Filed: November 12, 2004
    Date of Patent: September 5, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Ichiro Omura, Hiromichi Ohashi
  • Publication number: 20060145230
    Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.
    Type: Application
    Filed: December 5, 2005
    Publication date: July 6, 2006
    Inventors: Ichiro Omura, Wataru Saito, Tsuneo Ogura, Hiromichi Ohashi, Yoshihiko Saito, Kenichi Tokano
  • Patent number: 7067870
    Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.
    Type: Grant
    Filed: February 3, 2004
    Date of Patent: June 27, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Wataru Saito, Tsuneo Ogura, Hiromichi Ohashi, Yoshihiko Saito, Kenichi Tokano
  • Publication number: 20050263844
    Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semi-conductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.
    Type: Application
    Filed: July 28, 2005
    Publication date: December 1, 2005
    Inventors: Wataru Saito, Ichiro Omura, Hiromichi Ohashi
  • Patent number: 6940090
    Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semiconductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.
    Type: Grant
    Filed: August 6, 2003
    Date of Patent: September 6, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Ichiro Omura, Hiromichi Ohashi
  • Patent number: 6933544
    Abstract: A power semiconductor device including a non-doped GaN channel layer, an n-type Al0.2Ga0.8N barrier layer formed on the channel layer, a p-type Al0.1Ga0.9N semiconductor layer selectively formed on the barrier layer, a drain electrode positioned at one of both sides of the semiconductor layer and formed on the barrier layer, an insulating film formed on the barrier layer adjacent to the semiconductor layer between at least semiconductor layer and drain electrode, and a field plate electrode formed on the insulating film.
    Type: Grant
    Filed: October 19, 2004
    Date of Patent: August 23, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wataru Saito, Ichiro Omura, Hiromichi Ohashi
  • Publication number: 20050110042
    Abstract: A power semiconductor device including a non-doped GaN channel layer, an n-type Al0.2Ga0.8N barrier layer formed on the channel layer, a p-type Al0.1Ga0.9N semiconductor layer selectively formed on the barrier layer, a drain electrode positioned at one of both sides of the semiconductor layer and formed on the barrier layer, an insulating film formed on the barrier layer adjacent to the semiconductor layer between at least semiconductor layer and drain electrode, and a field plate electrode formed on the insulating film.
    Type: Application
    Filed: October 19, 2004
    Publication date: May 26, 2005
    Inventors: Wataru Saito, Ichiro Omura, Hiromichi Ohashi
  • Publication number: 20050087765
    Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semi-conductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.
    Type: Application
    Filed: November 12, 2004
    Publication date: April 28, 2005
    Inventors: Wataru Saito, Ichiro Omura, Hiromichi Ohashi
  • Publication number: 20040227211
    Abstract: A power semiconductor device includes a first semiconductor layer, a second semiconductor layer of a first conductivity type, first and second main electrodes, a control electrode and a third semiconductor layer. The second semiconductor layer is formed on the first semiconductor layer. The first and second main electrodes are formed on the second semiconductor layer separately from each other. The control electrode is formed on the second semiconductor layer between the first and second main electrodes. The third semiconductor layer is formed on the second semiconductor layer between the control electrode and the second main electrode.
    Type: Application
    Filed: August 6, 2003
    Publication date: November 18, 2004
    Inventors: Wataru Saito, Ichiro Omura, Hiromichi Ohashi
  • Publication number: 20040155287
    Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.
    Type: Application
    Filed: February 3, 2004
    Publication date: August 12, 2004
    Inventors: Ichiro Omura, Wataru Saito, Tsuneo Ogura, Hiromichi Ohashi, Yoshihiko Saito, Kenichi Tokano
  • Patent number: 6750508
    Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.
    Type: Grant
    Filed: June 28, 2001
    Date of Patent: June 15, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Wataru Saito, Tsuneo Ogura, Hiromichi Ohashi, Yoshihiko Saito, Kenichi Tokano
  • Publication number: 20040043565
    Abstract: A semiconductor device comprises a drain layer of first conductivity type, drift layers of first and second conductivity types on the drain layer, an insulating film between the drift layers and contacting the drift layers, a first base layer of second conductivity type on a surface of the drift layer of first conductivity type, a source layer of first conductivity type selectively provided on a surface of the first base layer of second conductivity type, a gate insulating film on the first base layer of second conductivity type between the source layer and the drift layer, a gate electrode on the gate insulating film, a second base layer of second conductivity type on a surface of the drift layer, a first main electrode on the drain layer, and a second main electrode on the source layer, the first base layer and the second base layer.
    Type: Application
    Filed: April 1, 2003
    Publication date: March 4, 2004
    Inventors: Masakazu Yamaguchi, Ichiro Omura, Wataru Saito, Takashi Shinohe, Hiromichi Ohashi
  • Patent number: 6534998
    Abstract: Disclosed is a semiconductor device capable of stabilizing a gate voltage at high voltage and high current, protecting the device from breakdown by preventing current nonuniformity and oscillations and the like, thereby improving reliability, and a method for controlling the semiconductor device.
    Type: Grant
    Filed: November 21, 2000
    Date of Patent: March 18, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Wolfgang Fichtner, Hiromichi Ohashi, Tsuneo Ogura, Hideaki Ninomiya
  • Publication number: 20020030237
    Abstract: A semiconductor element of this invention includes a drift layer of a first conductivity type formed on a semiconductor substrate of the first conductivity type, a well layer of a second conductivity type selectively formed in the surface of the drift layer, a source layer of the first conductivity type selectively formed in the surface of the well layer, a trench formed to reach at least the inside of the drift layer from the surface of the source layer through the well layer, a buried electrode formed in the trench through a first insulating film, and a control electrode formed on the drift layer, the well layer, and the source layer through a second insulating film.
    Type: Application
    Filed: June 28, 2001
    Publication date: March 14, 2002
    Inventors: Ichiro Omura, Wataru Saito, Tsuneo Ogura, Hiromichi Ohashi, Yoshihiko Saito, Kenichi Tokano
  • Patent number: 6323717
    Abstract: According to this invention, there is provided a drive apparatus for a power device having high- and low-voltage main electrodes and a control electrode, including a circuit for decreasing a voltage of the control electrode to a voltage of the control electrode which is not higher than a threshold voltage of the power device before a voltage between the high- and low-voltage main electrodes enters an overshoot region in a case where the power device is to be turned off. Therefore, electron injection can be stopped before the voltage between the main electrodes rises, the stability of the current density can be improved, and current concentration, oscillation, and the like can be prevented to improve reliability.
    Type: Grant
    Filed: May 17, 1999
    Date of Patent: November 27, 2001
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Suzuo Saito, Hiromichi Ohashi, Tomokazu Domon, Koichi Sugiyama, Simon Eicher, Tsuneo Ogura
  • Patent number: 6153896
    Abstract: Disclosed is a semiconductor device capable of stabilizing a gate voltage at high voltage and high current, protecting the device from breakdown by preventing current nonuniformity and oscillations and the like, thereby improving reliability, and a method for controlling the semiconductor device.
    Type: Grant
    Filed: March 13, 1998
    Date of Patent: November 28, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Wolfgang Fichtner, Hiromichi Ohashi, Tsuneo Ogura, Hideaki Ninomiya
  • Patent number: 6057636
    Abstract: The present invention provides a micro power switch comprising a cold cathode for emitting electrons, an anode for capturing the electrons emitted from the cold cathode, and a control electrode for controlling an amount of the electrons emitted from the cold cathode, wherein the cold cathode is made of material having a smaller electron emission barrier than the control electrode, the anode is applied with a positive potential in relation to the cold cathode, and the control electrode is applied with a potential equal to or lower than a potential of the cold cathode.
    Type: Grant
    Filed: September 16, 1997
    Date of Patent: May 2, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Tadashi Sakai, Tomio Ono, Naoshi Sakuma, Hiromichi Ohashi, Kazuya Nakayama
  • Patent number: 6037632
    Abstract: A semiconductor device is disclosed, which comprises a first main electrode, a second main electrode, a high-resistance semiconductor layer of first conductivity type interposed between the first main electrode and the second main electrode, and at least a buried layer of second conductivity type selectively formed in the semiconductor layer, extending at substantially right angles to a line connecting the first and second main electrodes, comprising a plurality strips functioning as current paths and set at a potential different from a potential of any other electrode when a depletion layer extending from a region near the first main electrode reaches the buried layer.
    Type: Grant
    Filed: November 5, 1996
    Date of Patent: March 14, 2000
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Ichiro Omura, Tomoki Inoue, Hiromichi Ohashi