Patents by Inventor Hiromichi Ohashi
Hiromichi Ohashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 6025622Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.Type: GrantFiled: June 25, 1998Date of Patent: February 15, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi, Yoshihiro Yamaguchi, Kiminori Watanabe, Thuneo Thukakoshi
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Patent number: 5977693Abstract: A micro-vacuum device comprises a substrates an emitter having a sharp end formed above the substrate, a gate electrode provided above the emitter, and an anode having cooling means provided oppositely to the substrate above the gate electrode.Type: GrantFiled: September 11, 1995Date of Patent: November 2, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Nakamoto, Hiromichi Ohashi
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Patent number: 5780887Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.Type: GrantFiled: June 14, 1994Date of Patent: July 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi, Yoshihiro Yamaguchi, Kiminori Watanabe, Thuneo Thukakoshi
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Patent number: 5747926Abstract: A ferroelectric cold cathode comprising a ferroelectric layer formed of a ferroelectric material and provided on its one surface with an emitter which is a projection having a sharp tip portion, a first electrode layer formed on one surface of the ferroelectric layer and having an opening allowing the sharp tip portion of the emitter to be exposed therethrough, and a second electrode layer formed on the other surface of the ferroelectric layer. When a voltage is applied between the first electrode and the second electrode, a dielectric polarization is reversed in the ferroelectric layer, resulting in the emission of electrons from the sharp tip portion of the emitter.Type: GrantFiled: March 8, 1996Date of Patent: May 5, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Masayuki Nakamoto, Hiromichi Ohashi
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Patent number: 5714775Abstract: A p-type emitter layer having a low resistivity is arranged on a bottom surface of an n-type base layer having a high resistivity. A p-type base layer is formed in a top surface of the n-type base layer. Trenches are formed in the p-type base layer and the n-type base layer such that each trench penetrates the p-type base layer and reaches down to a halfway depth in the n-type base layer. Inter-trench regions made of semiconductor are defined between the trenches. An n-type emitter layer having a low resistivity is formed in a surface of the p-type base layer to be in contact with the upper part of each trench. A gate electrode is buried via a gate insulating film in each trench. That side surface of each inter-trench region which faces the gate electrode consists of a {100} plane.Type: GrantFiled: April 19, 1996Date of Patent: February 3, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Tomoki Inoue, Ichiro Omura, Hiromichi Ohashi
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Patent number: 5286984Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.Type: GrantFiled: November 27, 1991Date of Patent: February 15, 1994Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi, Yoshihiro Yamaguchi, Kiminori Watanabe, Thuneo Thukakoshi
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Patent number: 5212396Abstract: A COM switching device includes an n.sup.+ -type layer formed on a p.sup.+ -type layer, p.sup.+ -type regions formed in the surface areas of an n.sup.- -type layer formed on the n.sup.+ -type layer, n.sup.+ -type regions formed in the surface areas of the p.sup.+ -type regions, and a gate electrode formed on an insulating layer over the surface areas of the p.sup.+ -type regions which lie between the n.sup.+ -type regions and the n.sup.- -type layer. The n.sup.+ -type layer is formed such that the amount of impurities per unit area is between 5.times.10.sup.13 cm.sup.-2 and 1.times.10.sup.15 cm.sup.-2, and the p.sup.+ -type layer is formed to have an impurity concentration between 2.times.10.sup.18 and 8.times.10.sup.18 cm.sup.-3.Type: GrantFiled: December 17, 1991Date of Patent: May 18, 1993Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi
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Patent number: 5093701Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.Type: GrantFiled: January 21, 1988Date of Patent: March 3, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi, Yoshihiro Yamaguchi, Kiminori Watanabe, Thuneo Thukakoshi
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Patent number: 5086323Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.Type: GrantFiled: June 10, 1991Date of Patent: February 4, 1992Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi, Yoshihiro Yamaguchi, Kiminori Watanabe, Thuneo Thukakoshi
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Patent number: 5028974Abstract: A semiconductor switching device includes a high resistance first base layer of n-type formed on a first emitter layer of p-type through a low resistance buffer layer of n.sup.+ -type, second base layer of p-type formed on the first base layer, second emitter layers of n.sup.+ -type separately formed on the second base layer, anode and cathode main electrodes formed in contact with the first and second emitter layers, and a gate electrode formed in contact with the second base layer. Part of the low resistance buffer layer is exposed to the surface of the first emitter layer and is made contact with the anode main electrode to constitute a shorting portion. The width of the shorting portion is set smaller than one tenth of that of the second emitter layer in a longitudinal direction.Type: GrantFiled: February 5, 1990Date of Patent: July 2, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Mituhiko Kitagawa, Tsuneo Ogura, Hiromichi Ohashi, Yoshinari Uetake, Yoshio Yokota, Kazuo Watanuki
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Patent number: 5006921Abstract: A semiconductor switching apparatus includes a member for radiating heat generated from semiconductor switching element chips and for reducing a thermal stress. The lengths of gate electrode wires are equally set. The semiconductor switching apparatus has a large capacity and good switching characteristics.Type: GrantFiled: March 31, 1989Date of Patent: April 9, 1991Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Ishizuka, Yasuyuki Yokono, Asako Matsuura, Yoshio Kamei, Hiromichi Ohashi, Mitsuhiko Kitagawa, Tomiya Sasaki, Shigeki Monma
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Patent number: 4928155Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.Type: GrantFiled: June 10, 1988Date of Patent: May 22, 1990Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi, Yoshihiro Yamaguchi, Kiminori Watanabe, Thuneo Thukakoshi
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Patent number: 4881120Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.Type: GrantFiled: November 4, 1987Date of Patent: November 14, 1989Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi, Yoshihiro Yamaguchi, Kiminori Watanabe, Thuneo Thukakoshi
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Patent number: 4791470Abstract: A reverse conducting gate turn-off thyristor device in which a gate turn-off thyristor and a reverse conduction diode are integrally formed in the same semiconductor wafer is constituted in such a manner that a part of a gate electrode is arranged in an isolation region that is sandwiched by the gate turn-off thyristor section and the reverse conduction diode section.Type: GrantFiled: June 22, 1987Date of Patent: December 13, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shinohe, Katsuhiko Takigami, Hiromichi Ohashi, Tsuneo Ogura, Masayuki Asaka
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Patent number: 4782372Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.Type: GrantFiled: February 26, 1987Date of Patent: November 1, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi, Yoshihiro Yamaguchi, Kiminori Watanabe, Thuneo Thukakoshi
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Patent number: 4738935Abstract: A method of manufacturing a compound semiconductor device has the steps of mirror-polishing a surface of each of two compound semiconductor substrates, bringing the mirror-polished surfaces of the two compound semiconductor substrates in contact with each other in a clean atmosphere and in a state wherein substantially no foreign substances are present therebetween, and annealing the compound semiconductor substrates which are in contact with each other so as to provide a bonded structure having a junction with excellent electrical characteristics at the interface.Type: GrantFiled: December 16, 1985Date of Patent: April 19, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Masaru Shimbo, Hiromichi Ohashi, Kazuyoshi Furukawa, Kiyoshi Fukuda
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Patent number: 4717940Abstract: An MIS controlled gate turn-off thyristor includes a pnpn structure comprised of a first emitter layer, a first base layer, a second base layer and a second emitter layer, and a turn-off MIS transistor for short-circuiting the second base layer to the second emitter layer. A low impurity concentration layer is formed on the second base layer and the second emitter layer is so formed that it extends, through the low impurity concentration layer, into the second base layer. The MIS transistor is formed on the surface portion of said low impurity concentration layer.Type: GrantFiled: February 13, 1987Date of Patent: January 5, 1988Assignee: Kabushiki Kaisha ToshibaInventors: Takashi Shinohe, Katsuhiko Takigami, Hiromichi Ohashi, Akio Nakagawa
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Patent number: 4700466Abstract: A method of manufacturing a semiconductor device, wherein a semiconductor wafer having a first impurity-doped layer and a second impurity-doped layer having a higher impurity concentration than that of the first impurity-doped layer is formed. A first silicon substrate, having a first impurity-doped layer and a third impurity-doped layer which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, is brought into contact with a second silicon substrate which has a higher impurity concentration than that of the first impurity-doped layer and the same conductivity type as that of the second impurity-doped layer, and whose surface is mirror-polished, so that the mirror-polished surfaces thereof are in contact with each other.Type: GrantFiled: February 3, 1986Date of Patent: October 20, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi, Tsuneo Ogura, Masaru Shimbo
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Patent number: 4689647Abstract: A COM switching device includes an n.sup.+ -type layer formed on a p.sup.+ -type layer, p.sup.+ -type regions formed in the surface areas of an n.sup.- -type layer formed on the n.sup.+ -type layer, n.sup.+ -type regions formed in the surface areas of the p.sup.+ -type regions, and a gate electrode formed on an insulating layer over the surface areas of the p.sup.+ -type regions which lie between the n.sup.+ -type regions and the n.sup.- -type layer. The n.sup.+ -type layer is formed such that the amount of impurities per unit area is 5.times.10.sup.13 cm.sup.-2 or more.Type: GrantFiled: April 30, 1986Date of Patent: August 25, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi
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Patent number: 4672407Abstract: A conductivity modulated MOSFET, having a semiconductor substrate of a first conductivity type, a semiconductor layer of a second conductivity type formed on the semiconductor substrate and having a high resistance, a base layer of the first conductivity type formed in the semiconductor layer, a source layer of the second conductivity type formed in the base layer, a gate electrode formed on a gate insulating film which is formed on a channel region, the channel region being formed in a surface of the base layer between the semiconductor layer and the source layer, a source electrode ohmic-contacting the source layer and the base layer, and a drain electrode formed on the surface of the semiconductor substrate opposite to the semiconductor layer, characterized in that the conductivity modulated MOSFET has a saturation current smaller than a latch-up current when a predetermined gate voltage is applied to the gate electrode.Type: GrantFiled: May 28, 1985Date of Patent: June 9, 1987Assignee: Kabushiki Kaisha ToshibaInventors: Akio Nakagawa, Hiromichi Ohashi, Yoshihiro Yamaguchi, Kiminori Watanabe, Thuneo Thukakoshi