Abstract: A semiconductor device includes multilayer interconnects and two variable resistance elements (22a, 22b) that are provided among the multilayer interconnects and that include first electrodes (5), second electrodes (10a, 10b), and variable resistance element films (9a, 9b) that are each interposed between first electrodes (5) and respective second electrodes (10a, 10b). Either the first electrodes (5) or the second electrodes (10a, 10b) of the two variable resistance elements (22a, 22b) are unified.

Abstract: A variable resistance element includes a first electrode, a second electrode and an ion conduction layer interposed between the first and second electrodes. The ion conduction layer contains an organic oxide containing at least oxygen and carbon. The carbon concentration distribution in the ion conduction layer is such that the carbon concentration in an area closer to the first electrode is greater than that in an area closer to the second electrode.

Abstract: Disclosed is a semiconductor device including a resistive change element between a first wiring and a second wiring, which are arranged in a vertical direction so as to be adjacent to each other, with an interlayer insulation film being interposed on a semiconductor substrate. The resistive change element includes a lower electrode, a resistive change element film made of a metal oxide and an upper electrode. Since the upper electrode on the resistive change element film is formed as part of a plug for the second wiring, a structure in which a side surface of the upper electrode is not in direct contact with the side surface of the metal oxide or the lower electrode is provided so that it is possible to realize excellent device characteristics, even when a byproduct is adhered to the side wall of the metal oxide or the lower electrode in the etching thereof.

Abstract: A resistance changing element according to the present invention comprises a first electrode (101) and a second electrode (103); and an ion conducting layer (102) that is formed between the first electrode (101) and the second electrode (103) and that contains at least oxygen and carbon.

Abstract: The objective of the present invention is to provide a semiconductor device provided with a resistance-variable element having sufficient switching property and exhibiting high reliability and high densification as well as good insulating property. The present invention provides a semiconductor device comprising a resistance-variable element provided within multiple wiring layers on a semiconductor substrate, wherein the resistance-variable element comprises a laminated structure in which a first electrode, a first ion-conductive layer of valve-metal oxide film, a second ion-conductive layer containing oxygen and a second electrode are laminated in this order, and the wiring of the multiple wiring layers also serves as the first electrode.

Abstract: A resistance-variable element as disclosed has high reliability, high densification, and good insulating properties. The device provides a resistance-variable element in which a first electrode including a metal primarily containing copper, an oxide film of valve-metal, an ion-conductive layer containing oxygen and a second electrode are laminated in this order.

Abstract: A method for manufacturing a semiconductor device, includes: forming an insulating film containing silicon, oxygen and carbon on at least one of a first substrate and a second substrate; and bonding the first substrate and the second substrate together, with the insulating film interposed therebetween. There can be provided a method capable of manufacturing a semiconductor device having high element density, high performance and high reliability, with high yield.

Abstract: A semiconductor device comprises a semiconductor substrate; a multilevel wiring layer structure on the semiconductor substrate; and a variable resistance element in the multilevel wiring layer structure, wherein the variable resistance element comprises a variable resistance element film whose resistance changes between a top electrode and a bottom electrode, wherein the multilevel wiring layer structure comprises at least a wiring electrically connected to the bottom electrode and a plug electrically connected to the top electrode, and wherein the wiring also serves as the bottom electrode.

Abstract: On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug.

Abstract: A memory cell of a semiconductor dynamic random access memory device requires a bit line contact hole open to a drain region of a cell transistor for connecting a bit line to the drain region and a node contact hole open to a source region for connecting a storage electrode of a stacked capacitor to the source region, and the bit line contact hole and the node contact hole are plugged with silicon layers; the silicon layers are epitaxially grown from the source and drain regions over an oxide-encapsulated gate electrode of the cell transistor so as to increase the contact areas; and the silicon layers are firstly anisotropically grown until reaching the upper surface of the oxide-encapsulated gate electrode, and, thereafter, isotropically grown so as to increase the contact areas.

Abstract: A natural oxide on an amorphous silicon exposed to a miniature contact hole is thermally decomposed in vacuum and an amorphous silicon is grown on the amorphous silicon without exposing to the atmosphere; the amorphous silicon is applied with heat so as to be epitaxially grown on a single crystal silicon beneath the amorphous silicon, thereby forming a conductive plug in the miniature contact hole.

Abstract: On a main surface of a silicon substrate of one conductivity type, a diffusion layer of the opposite conductivity type is formed, and the main surface of the silicon substrate is covered by an insulator film. The insulator film is formed with a contact hole which extends to reach the diffusion layer of the opposite conductivity type. A contact plug is provided in the contact hole. The contact plug fills the contact hole and comprises a first silicon layer of the opposite conductivity type directly connected to the diffusion layer of the opposite conductivity type, a silicon-germanium alloy layer of the opposite conductivity type directly contact to the first silicon layer, and a second silicon layer of the opposite conductivity type directly contact to the silicon-germanium alloy layer. Wiring is provided on the surface of the insulator film in direct contact to the contact plug.

Abstract: A silicon layer serving as a contact plug directly connected to a diffusion layer of a MOS transistor is provided. On a surface of an N.sup.- type diffusion layer in self-alignment with a silicon nitride layer spacer and a field oxide layer, an N.sup.+ type monocrystalline silicon layer formed by anisotropic selective epitaxial growth method is directly connected. The surface of the N.sup.+ type monocrystalline silicon layer is directly connected to an N.sup.+ type monocrystalline silicon layer formed by isotropic selective epitaxial growth.

Abstract: An inter-level insulating structure is formed by a lower silicon oxide layer, an upper silicon oxide layer and an air layer filling a gap between the lower silicon oxide layer and the upper silicon oxide layer, and the air layer decreases the effective dielectric constant so that a parasitic capacitance across the inter-level insulating structure is drastically decreased.

Abstract: A method is provided for forming an epitaxial silicon layer on a diffused region of a silicon substrate having an anisotropic ratio of more than 3:1 between the growth rate in the direction perpendicular to the substrate surface and the growth rate in the direction parallel to the substrate surface. The epitaxial silicon layer serves as a contact plug which does not contact an adjacent contact plug formed by the same process in order to obtain a reliable semiconductor memory device with a high throughput, which is free from short circuit failure.

Abstract: The present invention provides a test pattern and method for separately measuring a plug resistance and interfacial resistance of a contact resistance with high precision including the steps of: (a) providing on a semiconductor chip a test pattern as described above; (b) applying a predetermined voltage between the electrode pad patterns of one of a pair of first and second electrode pad patterns and a pair of third and fourth electrode pad patterns and measuring a current flowing between the electrode pad patterns of the one pair in an open state between the electrode pad patterns of the other pair; (c) repeating this measuring method between the electrode pad patterns of each pair; and (d) determining a first plug resistance of the first or fourth contact hole and a second plug resistance of the second or third contact hole from the voltage and the first to third currents.

Abstract: A test pattern for contact resistance, includes a contact hole section, and first to fourth electrode pad patterns connected to the contact hole section.