Abstract: Photoelectric conversion efficiency is improved.

Abstract: A solid-state imaging device includes a first semiconductor substrate, an isolation region, a charge holding section, and a charge accumulation section. The first semiconductor substrate is a substrate in which a photoelectric converter is provided for each of unit regions. The isolation region is provided to run through the first semiconductor substrate in a thickness direction and electrically isolates the unit regions from each other. The charge holding section is electrically coupled to the photoelectric converter and configured to receive signal charge from the photoelectric converter. The charge accumulation section is shared by two or more of the unit regions and is a section to which the signal charge is transferred from the photoelectric converter and the charge holding section of each of the unit regions sharing the charge accumulation section.

Abstract: A solid-state imaging device including: a semiconductor substrate having a first surface and a second surface opposed to each other, and including a photoelectric converter provided for each of pixel regions; an impurity diffusion region provided, for each of the pixel regions, in proximity to the first surface of the semiconductor substrate; and a contact electrode embedded in the semiconductor substrate from the first surface, and provided over and in contact with the impurity diffusion regions each provided for each of the pixel regions adjacent to each other.

Abstract: A solid-state imaging device including: a semiconductor substrate having a first surface and a second surface opposed to each other, and including a photoelectric converter provided for each of pixel regions; an impurity diffusion region provided, for each of the pixel regions, in proximity to the first surface of the semiconductor substrate; and a contact electrode embedded in the semiconductor substrate from the first surface, and provided over and in contact with the impurity diffusion regions each provided for each of the pixel regions adjacent to each other.

Abstract: Provided are an imaging device and a ranging device capable of reducing a chip size while suppressing diffraction of light to a light-shielding pixel region. The imaging device includes a semiconductor layer including an incident surface on which light is incident, a plurality of pixels provided on the semiconductor layer and arranged in parallel to the incident surface, and a reflection unit provided on the incident surface side of the semiconductor layer that reflects the light.

Abstract: A solid-state imaging element according to an aspect of the present disclosure includes a first semiconductor substrate (11), an insulating layer (46) and a second semiconductor substrate (21), a floating diffusion layer (FD) of the first semiconductor substrate (11), a transfer gate (TG) of the first semiconductor substrate (11), a first through wire (71) electrically connected to the floating diffusion layer (FD) and penetrating the insulating layer (46) and the second semiconductor substrate (21), a second through wire (72) electrically connected to the transfer gate (TG) and penetrating the insulating layer (46) and the second semiconductor substrate (21), a wiring layer (56) stacked on the second semiconductor substrate (21) and having a wiring electrically connected to the first through wire (71) or the second through wire (72), and an adjustment layer that is provided on the second semiconductor substrate (21) so as to be in contact with both or one of the first through wire (71) and the second through

Abstract: There is provided a solid-state imaging device that includes a photoelectric conversion unit, a transfer gate, a floating diffusion unit, and a transistor. The photoelectric conversion unit produces a charge according to incident light. The transfer gate has a columnar shape having an opening that is continuous in a vertical direction, and transfers the charge from the photoelectric conversion unit. The floating diffusion unit is formed extending to a region surrounded by the opening of the transfer gate, and converts the transferred charge into a voltage signal. The transistor is electrically connected to the floating diffusion unit via a diffusion layer.

Abstract: An imaging device (11) includes a plurality of photoelectric converters, a separation portion (22, 23), and a plurality of elements. The photoelectric converter is provided to a semiconductor substrate. The separation portion is provided between pixels (21Gr, 21Gb, 21R, 21B) each including the photoelectric converter, the separation portion extending up to a specified depth from a light entrance surface of the semiconductor substrate, the light entrance surface being on a side on which light enters the semiconductor substrate. The element is provided on an element forming surface that is on a side opposite to the side of the light entrance surface. A first depth is deeper than a second depth, the first depth being a depth of the separation portion (22) provided in a region in which the element is provided, the second depth being a depth of the separation portion (23) provided in a region in which the element is not provided.

Abstract: A solid-state imaging device includes a first semiconductor substrate, an isolation region, a charge holding section, and a charge accumulation section. The first semiconductor substrate is a substrate in which a photoelectric converter is provided for each of unit regions. The isolation region is provided to run through the first semiconductor substrate in a thickness direction and electrically isolates the unit regions from each other. The charge holding section is electrically coupled to the photoelectric converter and configured to receive signal charge from the photoelectric converter. The charge accumulation section is shared by two or more of the unit regions and is a section to which the signal charge is transferred from the photoelectric converter and the charge holding section of each of the unit regions sharing the charge accumulation section.

Abstract: A solid-state imaging device including: a semiconductor substrate having a first surface and a second surface opposed to each other, and including a photoelectric converter provided for each of pixel regions; an impurity diffusion region provided, for each of the pixel regions, in proximity to the first surface of the semiconductor substrate; and a contact electrode embedded in the semiconductor substrate from the first surface, and provided over and in contact with the impurity diffusion regions each provided for each of the pixel regions adjacent to each other.

Abstract: In a solid-state imaging device, the area is reduced while the charge transfer efficiency is improved. The solid-state imaging device includes a photoelectric conversion unit, a transfer gate, a floating diffusion unit, and a transistor. The photoelectric conversion unit produces a charge according to incident light. The transfer gate has a columnar shape having an opening that is continuous in a vertical direction, and transfers the charge from the photoelectric conversion unit. The floating diffusion unit is formed extending to a region surrounded by the opening of the transfer gate, and converts the transferred charge into a voltage signal. The transistor is electrically connected to the floating diffusion unit via a diffusion layer.

Abstract: According to one embodiment, a solid-state imaging device includes a semiconductor layer, a charge transfer region, a floating diffusion (FD), and a reading gate. The semiconductor layer is provided with a photoelectric conversion element. The charge transfer region is formed on a surface of the semiconductor layer over a charge accumulation region in the photoelectric conversion element. The FD is provided on the charge transfer region to hold a charge transferred from the charge accumulation region. The reading gate is provided on a side surface of the FD and a side surface of the charge transfer region via an insulating film.

Abstract: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.

Abstract: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.

Abstract: A semiconductor device including silicide layers with different thicknesses corresponding to diffusion layer junction depths, and a method of fabricating the same are provided. According to one aspect, there is provided a semiconductor device comprising a first semiconductor element device and a second semiconductor element device, wherein the first semiconductor element device includes a first gate electrode, first diffusion layers disposed to sandwich the first gate electrode, and having a first junction depth, and a first silicide layer disposed in the first diffusion layers and having a first thickness, and the second semiconductor element device includes a second gate electrode, second diffusion layers disposed to sandwich the second gate electrode, and having a second junction depth greater than the first junction depth, and a second silicide layer disposed in the second diffusion layers and having a second thickness greater than the first thickness.

Abstract: A semiconductor device according to one embodiment includes: a semiconductor substrate having a SRAM region; an N-type element region formed in the SRAM region on the semiconductor substrate and including N-type source/drain regions; a P-type element region formed in the SRAM region on the semiconductor substrate so as to be substantially parallel to the N-type element region and including P-type source/drain regions; P-type well contact connections and N-type well contact connections formed on both sides of the N-type and P-type element regions in a longitudinal direction outside the SRAM region on the semiconductor substrate, respectively; an element isolation region for isolating the N-type element region, the P-type element region, the P-type well contact connection and the N-type well contact connection; a P-type well continuously formed under the N-type element region and the P-type well contact connection in the semiconductor substrate, and an N-type well continuously formed under the P-type element re

Abstract: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.

Abstract: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.

Abstract: A semiconductor device including silicide layers with different thicknesses corresponding to diffusion layer junction depths, and a method of fabricating the same are provided. According to one aspect, there is provided a semiconductor device comprising a first semiconductor element device and a second semiconductor element device, wherein the first semiconductor element device includes a first gate electrode, first diffusion layers disposed to sandwich the first gate electrode, and having a first junction depth, and a first silicide layer disposed in the first diffusion layers and having a first thickness, and the second semiconductor element device includes a second gate electrode, second diffusion layers disposed to sandwich the second gate electrode, and having a second junction depth greater than the first junction depth, and a second silicide layer disposed in the second diffusion layers and having a second thickness greater than the first thickness.

Abstract: A data holding circuit includes a first data holding unit, a second data holding unit and a selection unit. In the first data holding unit, a probability of a soft error at a time when input data has a first level is lower than a probability of a soft error at a time when the input data has a second level. In the second data holding unit, a probability of a soft error at a time when the input data has the second level is lower than a probability of a soft error at a time when the input data has the first level. The selection unit selects an output from the first data holding unit when the input data has the first level, and selects an output from the second data holding unit when the input data has the second level.