Patents by Inventor Hironobu Fukui

Hironobu Fukui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20070097728
    Abstract: A data holding circuit includes a first data holding unit, a second data holding unit and a selection unit. In the first data holding unit, a probability of a soft error at a time when input data has a first level is lower than a probability of a soft error at a time when the input data has a second level. In the second data holding unit, a probability of a soft error at a time when the input data has the second level is lower than a probability of a soft error at a time when the input data has the first level. The selection unit selects an output from the first data holding unit when the input data has the first level, and selects an output from the second data holding unit when the input data has the second level.
    Type: Application
    Filed: June 1, 2006
    Publication date: May 3, 2007
    Inventor: Hironobu Fukui
  • Publication number: 20050116361
    Abstract: A semiconductor device with a metal oxide semiconductor (MOS) type transistor structure, which is used for, e.g. a static random access memory (SRAM) type memory cell, includes a part that is vulnerable to soft errors. In the semiconductor device with the MOS type transistor structure, an additional load capacitance is formed at the part that is vulnerable to soft errors.
    Type: Application
    Filed: March 26, 2004
    Publication date: June 2, 2005
    Inventor: Hironobu Fukui
  • Patent number: 6878579
    Abstract: An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.
    Type: Grant
    Filed: August 13, 2004
    Date of Patent: April 12, 2005
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Ohuchi, Hironobu Fukui
  • Publication number: 20050012088
    Abstract: An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.
    Type: Application
    Filed: August 13, 2004
    Publication date: January 20, 2005
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya Ohuchi, Hironobu Fukui
  • Patent number: 6791106
    Abstract: An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.
    Type: Grant
    Filed: April 23, 2003
    Date of Patent: September 14, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Kazuya Ohuchi, Hironobu Fukui
  • Patent number: 6746943
    Abstract: A semiconductor device has a semiconductor substrate, a first transistor having a first gate electrode formed of a polycrystalline silicon germanium film as formed above said semiconductor substrate, and a second transistor having a second gate electrode which is formed of a polycrystalline silicon germanium film as formed above the semiconductor substrate and which is different in concentration of germanium from the first gate electrode.
    Type: Grant
    Filed: June 12, 2003
    Date of Patent: June 8, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Takayanagi, Hironobu Fukui
  • Patent number: 6696735
    Abstract: A semiconductor device according to one aspect of the present invention, is a semiconductor device comprising: a first MOS field effect transistor of an n-type including a first oxynitride film as a first gate insulator film; and a second MOS field effect transistor of a p-type including a second oxynitride film as a second gate insulator film, the second MOS field effect transistor being disposed adjacent to the first MOS field effect transistor; wherein a concentration of nitrogen in the first gate insulator film is different form that in the second gate insulator film.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: February 24, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hironobu Fukui
  • Publication number: 20030207555
    Abstract: A semiconductor device has a semiconductor substrate, a first transistor having a first gate electrode formed of a polycrystalline silicon germanium film as formed above said semiconductor substrate, and a second transistor having a second gate electrode which is formed of a polycrystalline silicon germanium film as formed above the semiconductor substrate and which is different in concentration of germanium from the first gate electrode.
    Type: Application
    Filed: June 12, 2003
    Publication date: November 6, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Mariko Takayanagi, Hironobu Fukui
  • Publication number: 20030201493
    Abstract: An aspect of the present invention includes a first conductive type semiconductor region; a gate electrode formed on the first conductive type semiconductor region; a channel region formed immediately below the gate electrode in the first conductive type semiconductor region; and a second conductive type first diffusion layer constituting source/drain regions formed at opposite sides of the channel region in the first conductive type semiconductor region, the gate electrode being formed of polycrystalline silicon-germanium, in which a germanium concentration is continuously increased from a drain region side to a source region side, and an impurity concentration immediately below the gate electrode in the first conductive type semiconductor region being continuously increased from the source region side to the drain region side in accordance with the germanium concentration in the gate electrode.
    Type: Application
    Filed: April 23, 2003
    Publication date: October 30, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Kazuya Ohuchi, Hironobu Fukui
  • Patent number: 6600212
    Abstract: A semiconductor device has a semiconductor substrate, a first transistor having a first gate electrode formed of a polycrystalline silicon germanium film as formed above said semiconductor substrate, and a second transistor having a second gate electrode which is formed of a polycrystalline silicon germanium film as formed above the semiconductor substrate and which is different in concentration of germanium from the first gate electrode.
    Type: Grant
    Filed: February 26, 2002
    Date of Patent: July 29, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mariko Takayanagi, Hironobu Fukui
  • Publication number: 20030116811
    Abstract: A semiconductor device according to one aspect of the present invention, is a semiconductor device comprising: a first MOS field effect transistor of an n-type including a first oxynitride film as a first gate insulator film; and a second MOS field effect transistor of a p-type including a second oxynitride film as a second gate insulator film, the second MOS field effect transistor being disposed adjacent to the first MOS field effect transistor; wherein a concentration of nitrogen in the first gate insulator film is different form that in the second gate insulator film.
    Type: Application
    Filed: February 27, 2002
    Publication date: June 26, 2003
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hironobu Fukui
  • Publication number: 20020130393
    Abstract: A semiconductor device has a semiconductor substrate, a first transistor having a first gate electrode formed of a polycrystalline silicon germanium film as formed above said semiconductor substrate, and a second transistor having a second gate electrode which is formed of a polycrystalline silicon germanium film as formed above the semiconductor substrate and which is different in concentration of germanium from the first gate electrode.
    Type: Application
    Filed: February 26, 2002
    Publication date: September 19, 2002
    Inventors: Mariko Takayanagi, Hironobu Fukui