Patents by Inventor Hironobu Miyamoto

Hironobu Miyamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160204243
    Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.
    Type: Application
    Filed: March 24, 2016
    Publication date: July 14, 2016
    Inventors: Takashi INOUE, Toshiyuki TAKEWAKI, Tatsuo NAKAYAMA, Yasuhiro OKAMOTO, Hironobu MIYAMOTO
  • Patent number: 9384124
    Abstract: According to one embodiment, a data storage device includes a first controller, a second controller, and a third controller. The first controller performs a control operation of writing data of a first data unit to a storage area in a flash memory and reading the data of the first data unit from the storage area. The second controller carries out migration processing of measuring a data amount of valid data stored in storage areas of a second data unit that is a data erase processing unit.
    Type: Grant
    Filed: December 19, 2012
    Date of Patent: July 5, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Taichiro Yamanaka, Yoko Masuo, Hironobu Miyamoto
  • Publication number: 20160170642
    Abstract: A memory system according to an embodiment includes a non-volatile memory and a controller configured to control the non-volatile memory. The controller includes an interface and a control unit. The interface receives, from a host, a first instruction to change a performance of the memory system as a performance control instruction. The control unit controls the memory system on the basis of the performance control instruction such that the number of parallel operations of parallel operating units which are operated in parallel in the memory system is changed.
    Type: Application
    Filed: March 12, 2015
    Publication date: June 16, 2016
    Inventors: Hironobu Miyamoto, Maoko Oyamada, Kenichiro Suzuki, Yoshihisa Kojima
  • Patent number: 9362401
    Abstract: A semiconductor device includes a substrate, a buffer layer provided on the substrate, a channel layer provided on the buffer layer, an electron supply layer provided on the channel layer, a first contact hole provided on the electron supply layer, a source electrode that is formed within the first contact hole, and electrically connected to the electron supply layer, a second contact hole provided on the electron supply layer, a drain electrode that is formed within the second contact hole, and electrically connected to the electron supply layer, a gate electrode provided between the source electrode and the drain electrode, a second insulating film that is formed to cover the gate electrode, a strain relaxation film that is formed over the second insulating film above the gate electrode, a third insulating film that is formed to cover the source electrode, the drain electrode, and the strain relaxation film, and an organic film that is formed over the third insulating film.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: June 7, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Takewaki, Hironobu Miyamoto
  • Patent number: 9361201
    Abstract: According to one embodiment, a memory system includes a NAND-type flash memory and a memory controller. The memory controller includes a monitoring module and a determination module. The monitoring module acquires an elapsed time from the start of data erase of a first block in the NAND-type flash memory. The determination module determines whether the elapsed time has exceeded a reference time before completion of the data write in the first block.
    Type: Grant
    Filed: January 24, 2013
    Date of Patent: June 7, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Yoko Masuo, Hironobu Miyamoto
  • Publication number: 20160133715
    Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.
    Type: Application
    Filed: December 29, 2015
    Publication date: May 12, 2016
    Applicant: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Takashi Inoue, Tatsuo Nakayama, Ryohei Nega, Masaaki Kanazawa, Hironobu Miyamoto
  • Patent number: 9337325
    Abstract: A method for manufacturing a semiconductor device includes forming a buffer layer made of a nitride semiconductor, forming a channel layer made of a nitride semiconductor over the buffer layer, forming a barrier layer made of a nitride semiconductor over the channel layer, forming a cap layer made of a nitride semiconductor over the barrier layer, forming a gate insulating film so as to in contact with the cap layer; and forming a gate electrode over the gate insulating film, wherein compression strains are generated at an interface between the cap layer and the barrier layer and an interface between the channel layer and the buffer layer and a tensile strain is generated at an interface between the barrier layer and the channel layer by controlling compositions of the cap layer, the barrier layer, the channel layer, and the buffer layer.
    Type: Grant
    Filed: March 28, 2014
    Date of Patent: May 10, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Inoue, Tatsuo Nakayama, Yasuhiro Okamoto, Hironobu Miyamoto
  • Patent number: 9306051
    Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has, over a substrate thereof, a first buffer layer (GaN), a second buffer layer (AlGaN), a channel layer, and a barrier layer, a trench penetrating through the barrier layer and reaching the middle of the channel layer, a gate electrode placed in the trench via a gate insulating film, and a source electrode and a drain electrode formed on both sides of the gate electrode respectively. By a coupling portion in a through-hole reaching the first buffer layer, the buffer layer and the source electrode are electrically coupled to each other. Due to a two-dimensional electron gas produced in the vicinity of the interface between these two buffer layers, the semiconductor device can have an increased threshold voltage and improved normally-off characteristics.
    Type: Grant
    Filed: January 6, 2015
    Date of Patent: April 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yoshinao Miura, Tatsuo Nakayama, Takashi Inoue, Hironobu Miyamoto
  • Patent number: 9306027
    Abstract: The characteristics of a semiconductor device are improved. A semiconductor device is formed so as to have a channel layer formed over a substrate, a barrier layer, a trench penetrating through the barrier layer in an opening region, and reaching some point of the channel layer, a gate electrode arranged in the trench via a gate insulation film, and an insulation film formed over the barrier layer outside the opening region. Then, the insulation film has a lamination structure of a Si-rich silicon nitride film, and a N-rich silicon nitride film situated thereunder. Thus, the upper layer of the insulation film is set as the Si-rich silicon nitride film. This enables the improvement of the breakdown voltage, and further, enables the improvement of the etching resistance. Whereas, the lower layer of the insulation film is set as the N-rich silicon nitride film. This can suppress collapse.
    Type: Grant
    Filed: November 20, 2014
    Date of Patent: April 5, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Takashi Inoue, Toshiyuki Takewaki, Tatsuo Nakayama, Yasuhiro Okamoto, Hironobu Miyamoto
  • Publication number: 20160064538
    Abstract: The characteristics of a semiconductor device are improved. A semiconductor device has a potential fixed layer containing a p type impurity, a channel layer, and a barrier layer, formed over a substrate, and a gate electrode arranged in a trench penetrating through the barrier layer, and reaching some point of the channel layer via a gate insulation film. Source and drain electrodes are formed on opposite sides of the gate electrode. The p type impurity-containing potential fixed layer has an inactivated region containing an inactivating element such as hydrogen between the gate and drain electrodes. Thus, while raising the p type impurity (acceptor) concentration of the potential fixed layer on the source electrode side, the p type impurity of the potential fixed layer is inactivated on the drain electrode side. This can improve the drain-side breakdown voltage while providing a removing effect of electric charges by the p type impurity.
    Type: Application
    Filed: August 27, 2015
    Publication date: March 3, 2016
    Applicant: RENESAS ELECTRONICS CORPORATION
    Inventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Ichiro MASUMOTO, Yasuhiro OKAMOTO, Shinichi MIYAKE, Hiroshi KAWAGUCHI
  • Patent number: 9269803
    Abstract: The reliability of a field effect transistor made of a nitride semiconductor material is improved. An ohmic electrode includes a plurality of unit electrodes isolated to be separated from each other. With this configuration, an on-state current can be prevented from flowing in the unit electrodes in a y-axial direction (negative direction). Further, in the respective unit electrodes, a current density of the on-state current flowing in the y-axial direction (negative direction) can be prevented from increasing. As a result, an electromigration resistance of the ohmic electrode can be improved.
    Type: Grant
    Filed: July 9, 2013
    Date of Patent: February 23, 2016
    Assignee: Renesas Electronics Corporation
    Inventors: Yasuhiro Okamoto, Takashi Inoue, Tatsuo Nakayama, Ryohei Nega, Masaaki Kanazawa, Hironobu Miyamoto
  • Publication number: 20160011937
    Abstract: In a semiconductor memory device of an embodiment, a controller writes write data and first address management information including address information of the write data to a memory, and performs, when an error occurs in any of the write data read from the memory, an error correction process to an error correction group including the write data and the first address management information. The controller generates, when a read error is detected within a process target error correction group, second address management information including address information of write data within the process target error correction group and error position information indicative of a position of the read error, and writes invalid data and the second address management information to erased condition areas within areas to be written of the process target error correction group.
    Type: Application
    Filed: September 8, 2014
    Publication date: January 14, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hironobu MIYAMOTO, Ryoichi Kato, Tomonori Masuo
  • Publication number: 20160005846
    Abstract: A semiconductor device includes a first semiconductor layer, a second semiconductor layer formed over the first semiconductor layer, a gate insulating film contacting the second semiconductor layer, and a gate electrode facing the second semiconductor layer via the gate insulating film. The first semiconductor layer includes an Alx?1-xN layer (? includes Ga or In, and 0<x<1), and the second semiconductor layer includes an Aly?1-yN layer (0?y<1), in which y of the Aly?1-yN layer forming the second semiconductor layer increases at least in a region under the gate electrode as a position where y is measured approaches the first semiconductor layer.
    Type: Application
    Filed: August 18, 2015
    Publication date: January 7, 2016
    Inventors: Yasuhiro OKAMOTO, Tatsuo NAKAYAMA, Takashi INOUE, Hironobu MIYAMOTO
  • Publication number: 20150339198
    Abstract: In a semiconductor memory device of an embodiment, a backup section writes backup data to a memory. The backup data corresponds to management data which associates identification data of data written to the memory with a write position of the data. A first generator generates update data indicating an updating state when the management data is updated after the backup data is written to the memory. A second generator generates update accumulated data including the update data and past update data which has been generated before the update data and written to the memory. A writer writes the update accumulated data to the memory. A restoration section restores the management data based on the backup data read from the memory and the update accumulated data.
    Type: Application
    Filed: September 4, 2014
    Publication date: November 26, 2015
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Ryoichi KATO, Hironobu Miyamoto, Tomonori Masuo, Tatsuya Sumiyoshi, Yuuichirou Gunji, Jun Shinohara
  • Publication number: 20150270394
    Abstract: A semiconductor device includes a substrate, a buffer layer provided on the substrate, a channel layer provided on the buffer layer, an electron supply layer provided on the channel layer, a first contact hole provided on the electron supply layer, a source electrode that is formed within the first contact hole, and electrically connected to the electron supply layer, a second contact hole provided on the electron supply layer, a drain electrode that is formed within the second contact hole, and electrically connected to the electron supply layer, a gate electrode provided between the source electrode and the drain electrode, a second insulating film that is formed to cover the gate electrode, a strain relaxation film that is formed over the second insulating film above the gate electrode, a third insulating film that is formed to cover the source electrode, the drain electrode, and the strain relaxation film, and an organic film that is formed over the third insulating film.
    Type: Application
    Filed: June 8, 2015
    Publication date: September 24, 2015
    Inventors: Toshiyuki TAKEWAKI, Hironobu MIYAMOTO
  • Patent number: 9123739
    Abstract: A semiconductor device includes: a first nitride semiconductor layer; a second nitride semiconductor layer formed over the first nitride semiconductor layer; and a gate electrode facing the second nitride semiconductor layer via a gate insulating film. Because the second nitride semiconductor layer is formed by stacking plural semiconductor layers with their Al composition ratios different from each other, the Al composition ratio of the second nitride semiconductor layer changes stepwise. The semiconductor layers forming the second nitride semiconductor layer are polarized in the same direction so that, among the semiconductor layers, a semiconductor layer nearer to the gate electrode has higher (or lower) intensity of polarization.
    Type: Grant
    Filed: July 12, 2012
    Date of Patent: September 1, 2015
    Assignee: RENESAS ELECTRONICS CORPORATION
    Inventors: Yasuhiro Okamoto, Tatsuo Nakayama, Takashi Inoue, Hironobu Miyamoto
  • Publication number: 20150221757
    Abstract: Characteristics of a semiconductor device are improved. The semiconductor device is configured to provide a trench that penetrates a barrier layer, and reaches a middle portion of a channel layer among an n+ layer, an n-type layer, a p-type layer, the channel layer, and the barrier layer which are formed above a substrate, a gate electrode arranged within the groove through a gate insulating film, and a source electrode and a drain electrode which are formed above the barrier layer on both sides of the gate electrode. The n-type layer and the drain electrode are electrically coupled to each other by a connection portion that reaches the n+ layer. The p-type layer and the source electrode are electrically coupled to each other by a connection portion that reaches the p-type layer. A diode including a p-type layer and an n-type layer is provided between the source electrode and the drain electrode, to thereby prevent the breaking of an element caused by an avalanche breakdown.
    Type: Application
    Filed: January 26, 2015
    Publication date: August 6, 2015
    Inventors: Tatsuo NAKAYAMA, Hironobu Miyamoto, Yasuhiro Okamoto, Yoshinao Miura, Takashi Inoue
  • Publication number: 20150221758
    Abstract: To provide a semiconductor device having improved characteristics. The semiconductor device has, over a substrate thereof, a first buffer layer (GaN), a second buffer layer (AlGaN), a channel layer, and a barrier layer, a trench penetrating through the barrier layer and reaching the middle of the channel layer, a gate electrode placed in the trench via a gate insulating film, and a source electrode and a drain electrode formed on both sides of the gate electrode respectively. By a coupling portion in a through-hole reaching the first buffer layer, the buffer layer and the source electrode are electrically coupled to each other. Due to a two-dimensional electron gas produced in the vicinity of the interface between these two buffer layers, the semiconductor device can have an increased threshold voltage and improved normally-off characteristics.
    Type: Application
    Filed: January 6, 2015
    Publication date: August 6, 2015
    Applicant: Renesas Electronics Corporation
    Inventors: Yoshinao MIURA, Tatsuo NAKAYAMA, Takashi INOUE, Hironobu MIYAMOTO
  • Patent number: 9070661
    Abstract: The reliability of a power MISFET made of a nitride semiconductor material is improved. A strain relaxation film is disposed between a polyimide film and a gate electrode, to suppress a stress exerted on an electron supply layer and a channel layer from the polyimide film, and suppress a stress strain generated in the electron supply layer and the channel layer. As a result, a change in channel electron concentration in the channel layer is suppressed to prevent a threshold voltage or an on-resistance of the power MISFET from fluctuating.
    Type: Grant
    Filed: July 31, 2014
    Date of Patent: June 30, 2015
    Assignee: Renesas Electronics Corporation
    Inventors: Toshiyuki Takewaki, Hironobu Miyamoto
  • Publication number: 20150171204
    Abstract: Characteristics of a semiconductor device are improved. A semiconductor device includes a potential fixing layer, a channel underlayer, a channel layer, and a barrier layer formed above a substrate, a trench that penetrates the barrier layer and reaches as far as a middle of the channel layer, gate electrode disposed by way of an insulation film in the trench, and a source electrode and a drain electrode formed respectively over the barrier layer on both sides of the gate electrode. A coupling portion inside the through hole that reaches as far as the potential fixing layer electrically couples the potential fixing layer and the source electrode. This can reduce fluctuation of the characteristics such as a threshold voltage and an on-resistance.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 18, 2015
    Inventors: Tatsuo NAKAYAMA, Hironobu MIYAMOTO, Yasuhiro OKAMOTO, Yoshinao MIURA, Takashi INOUE