Abstract: A simulation device and simulation program are provided that can be suitably applied to a manufacturing process including a plurality of processing steps. The simulation device is provided for simulating the manufacturing process including a first processing step using a first mask, and a second processing step using a second mask. The simulation device includes first obtaining means for obtaining a first intensity distribution generated over a substrate of interest for processing by the first mask, second obtaining means for obtaining a second intensity distribution generated over the substrate by the second mask, and revising means for revising an intensity of a region in the first intensity distribution to be processed by the second mask, to a value regarded as a region not to be processed, based on the second intensity distribution.

Abstract: A mask data verification apparatus compares a design layout with design layout patterns stored in an existing-type library and extracts a design layout pattern found to be neither equal nor similar as a new-type design layout pattern. The mask data verification apparatus generates mask data using OPC/RET with reference to a new design layout pattern stored in a new-type library and performs post-verification. The mask data verification apparatus can previously verify a new design layout pattern, shorten a semiconductor device manufacturing period, ensure efficient development, and improve a manufacturing yield.

Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.

Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.

Abstract: The present invention provides a lithography verification apparatus which executes high-precision lithography verification in consideration of the effects of individual errors integrated. Various information (simulation result, error standard, etc.) are input. A variation distribution value is calculated. The variation distribution value and a variation distribution error standard are compared to determine whether the variation distribution value is smaller than the error standard. The variation distribution error standard is a standard for a value or the like related to a standard deviation or the like for a dimensional displacement. When it is determined that the variation distribution value is smaller than the error standard, an error is determined not to exist, and the processing is ended. When it is determined that the variation distribution value is not smaller than the error standard, an error is determined to exist, and an error list and a variation distribution value are outputted.

Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.

Abstract: A mask data verification apparatus compares a design layout with design layout patterns stored in an existing-type library and extracts a design layout pattern found to be neither equal nor similar as a new-type design layout pattern. The mask data verification apparatus generates mask data using OPC/RET with reference to a new design layout pattern stored in a new-type library and performs post-verification. The mask data verification apparatus can previously verify a new design layout pattern, shorten a semiconductor device manufacturing period, ensure efficient development, and improve a manufacturing yield.

Abstract: The present invention provides a lithography verification apparatus which executes high-precision lithography verification in consideration of the effects of individual errors integrated. Various information (simulation result, error standard, etc.) are input. A variation distribution value is calculated. The variation distribution value and a variation distribution error standard are compared to determine whether the variation distribution value is smaller than the error standard. The variation distribution error standard is a standard for a value or the like related to a standard deviation or the like for a dimensional displacement. When it is determined that the variation distribution value is smaller than the error standard, an error is determined not to exist, and the processing is ended. When it is determined that the variation distribution value is not smaller than the error standard, an error is determined to exist, and an error list and a variation distribution value are outputted.

Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.

Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.

Abstract: An object of the present invention is to reduce processing time and manufacturing cost for a semiconductor device including a logic circuit. To accomplish the above object, an area (114) for forming a logic circuit includes a first area (114b, 170) which is subjected to optical proximity correction with predetermined accuracy, and a second area (114a, 180) which is subjected to optical proximity correction with accuracy lower than said predetermined accuracy. Especially, the first area (114b, 170) includes a gate interconnection line (172) which acts as a transistor, and the second area (114a, 180) includes a dummy layout pattern (182) which does not act as a transistor.

Abstract: To provide a semiconductor device manufacturing method using double patterning, in which layout patterns are distributed avoiding yield reduction factors. The semiconductor device manufacturing method includes the steps of: preparing a plurality of masks for use in the double patterning; and performing the double patterning using the plurality of masks. The step of preparing the plurality of masks includes a step of distributing a group of layout patterns to the plurality of masks, in accordance with characteristics of exposure steps respectively using the plurality of masks, and in consideration of size of the layout patterns.

Abstract: A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.

Abstract: A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.

Abstract: A layout pattern generating unit within a lithography process margin evaluating apparatus generates a plurality of design layout patterns, using an analysis condition and information stored in a layout pattern template holding unit. In addition, a simulation condition generating unit generates a plurality of simulation conditions, using the analysis condition and information stored in a simulation condition template holding unit. A simulation unit generates a plurality of actual layout patterns, using a generated condition. Thus, the lithography process margin evaluating apparatus can reduce operational burden and improve accuracy.

Abstract: A semiconductor integrated circuit layout figure, inclusive of dimensional accuracy depending on the pattern shape, is efficiently verified with high accuracy. A layout verifying method for verifying whether or not a layout figure conforms to a design rule on the basis of vector data includes a reference vector classifying step for selecting and classifying a reference vector which serves as a reference for verification among vectors corresponding to sides, a verification object vector classifying step for selecting and classifying a object vector to be verified among the vectors corresponding to the sides and a verifying step for verifying a distance between each reference vector and the object vector to be verified selected among the vectors to be verified classified in correspondence with the direction of the reference vector.

Abstract: Sampling points are generated selectively in a prescribed portion other than the pattern edge portion of a layout pattern used in a semiconductor manufacturing process based on an input that is data of the layout pattern. Simulation results of a pattern to be generated from the layout pattern are obtained for the respective sampling points. Pattern distortion amounts in the portion other than the pattern edge portion are detected by comparing the data of the layout pattern and the simulation results for the respective sampling points.

Abstract: A finished pattern that will be formed based on a design layout pattern in a semiconductor manufacturing process is predicted, and the outline of the predicted finished pattern is converted into a polygon. On the other hand, test reference patterns are formed based on the design layout pattern. A pattern distortion in the predicted finished pattern is detected by comparing the polygonized predicted finished pattern with the test referencepatterns. In converting the predicted finished pattern into a polygon, the number of apices of the polygon is reduced. Two kinds of test reference patterns are formed: an upper limit test reference pattern obtained by reducing the design layout pattern and defining an allowable upper limit and a lower limit test reference pattern obtained by enlarging the design layout pattern and defining an allowable lower limit.

Abstract: Sampling points are generated selectively in a prescribed portion other than the pattern edge portion of a layout pattern used in a semiconductor manufacturing process based on an input that is data of the layout pattern. Simulation results of a pattern to be generated from the layout pattern are obtained for the respective sampling points. Pattern distortion amounts in the portion other than the pattern edge portion are detected by comparing the data of the layout pattern and the simulation results for the respective sampling points.

Abstract: A pattern distortion correction device which performs distortion correction of a layout pattern is provided, considering not only an edge shift value but also a process margin. The pattern distortion correction device comprises a finished pattern anticipation section anticipating a finished pattern of a layout pattern, an edge shift value measure section measuring an edge shift value which is a gap between an anticipated finished pattern and a standard pattern, a process margin measure section measuring a process margin of the anticipated finished pattern, a measure result determination section determining whether or not a measured edge shift value and a measured process margin satisfy a determination standard, and a layout pattern temporary correction section correcting the layout pattern so as to satisfy the determination standard based on a determination result by the measure result determination section.