Abstract: A memory system in an embodiment having a host and a memory card, including: a plurality of semiconductor memory cells, each cell being configured to store N-bit coded data based on threshold voltage distributions; an LLR table storage section configured to store a first LLR table that consists of normal LLR data corresponding to predetermined threshold voltages and a second LLR table that consists of LLR data such that two LLRs at each location corresponding to each location in the first LLR table at which a sign is inverted between two adjacent LLRs are “0”; and a decoder configured to perform decoding processing through probability-based repeated calculations using an LLR.

Abstract: A controller includes a generation unit configured to aggregate comparison results between second threshold voltage levels held in the memory cells and predetermined third threshold voltage levels, and generate a histogram of the second threshold voltage levels, an estimation unit configured to estimate statistical parameter of a distribution of the second threshold voltage levels with respect to a first threshold voltage level according to writing data, based on the histogram, and a determination unit configured to determine a fifth threshold voltage level defining a boundary of a fourth threshold voltage level indicating a read result of the memory cells from the third threshold voltage levels based on the statistical parameter in such a manner that mutual information amount between the first threshold voltage level and the fourth threshold voltage level becomes maximum.

Abstract: In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.

Abstract: Receiving-apparatus employed in MIMO-system includes space-filtering-unit configured to separate receive-signals to signal of first-data-sequence and signal of second-data-sequence on basis of estimation result, provisional-decoding-unit configured to LDPC-decode signal of first-data-sequence and signal of second-data-sequence with check-matrices which is modified in different-forms by fundamental-row-operation from each other, to obtain provisional-likelihood-ratio for first-data-sequence and second-data-sequence, provisional-output-unit configured to output provisional-first-data-sequence and provisional-second-data-sequence on the basis of provisional-likelihood-ratio for first-data-sequence and second-data-sequence respectively, replica-signal-generation-unit configured to generate replica-signal, on basis of provisional-first-data-sequence and provisional-second-data-sequence and estimation-result of propagation-path-estimation-unit, soft-decision-outputting-unit configured to obtain receive-likelihood-v

Abstract: In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: Before data is transmitted from a plurality of antennas, a plurality of known symbol sequences are transmitted from these antennas. Each known symbol sequence contains a plurality of known symbols having different subcarrier arrangements. Known symbols transmitted from different antennas have different subcarrier arrangements.

Abstract: There is provided with a decoding apparatus for decoding a low-density parity check code defined by a parity check matrix, includes: a first operation unit configured to carry out a row operation for each row of the parity check matrix; a calculation unit configured to calculate a reliability coefficient with respect to establishment of a parity check equation defined by said each row, respectively; a second operation unit configured to carry out a column operation for said each row; and a controller configured to iteratively execute one set which includes respective processing by the first operation unit, the calculation unit and the second operation unit and omit the processing by the first operation unit and the calculation unit for a row for which the reliability coefficient has satisfied a threshold.

Abstract: In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.

Abstract: A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information of N bits (N?2) in accordance with variations in threshold voltage. A parity data adder circuit adds parity data for error correction to every certain data bits to be stored in the memory cell array. A frame converter circuit uniformly divides frame data containing the data bits and the parity data into N pieces of subframe data. A programming circuit stores the subframe data divided into N pieces in respective N sub-pages formed corresponding to the information of N bits.

Abstract: Before data is transmitted from a plurality of antennas, a plurality of known symbol sequences are transmitted from these antennas. Each known symbol sequence contains a plurality of known symbols having different subcarrier arrangements. Known symbols transmitted from different antennas have different subcarrier arrangements.

Abstract: In a memory cell array, memory cells enabled to store plural-bit data are arranged in matrix. The bit-line control circuit is connected to bit-lines to control the bit-lines. A word line control circuit applies a plural-bit data read voltage as a word line voltage to the word line. The plural-bit data read voltage is larger than an upper limit of one of plural threshold voltage distributions and smaller than a lower limit of another threshold voltage distribution. Furthermore, it applies a soft-value read voltage as a word line voltage to the word line. The soft-value read voltage is smaller than an upper limit of a threshold voltage distribution and larger than a lower limit thereof. The likelihood calculation circuit calculates likelihood of the plural-bit data stores in the memory cells based on the soft-value.

Abstract: A non-volatile semiconductor memory device comprises a memory cell array including a plurality of memory cells arrayed capable of storing information in accordance with variations in threshold voltage. A likelihood calculator has a plurality of likelihood calculation algorithms for deriving a likelihood value about a stored data bit from a threshold value read out of the memory cell. An error correction unit executes error correction through iterative processing using the likelihood value obtained at the likelihood calculator. A likelihood calculator controller changes among the likelihood calculation algorithms in the likelihood calculator based on a certain value of the number of iterations in the iterative processing obtained from the error correction unit.

Abstract: This memory device comprises a word-line control circuit applying a read voltage and a soft-value read voltage as a word line voltage to a word line to generate soft-values. The soft-value read voltage is between an upper limit and a lower limit of each of plural threshold voltage distributions. A likelihood calculation circuit calculates a likelihood value of data stored in a memory cell based on the soft-value. An error correction circuit executes data error correction for the data read from the memory cell based on the likelihood value. A refresh control circuit controls a timing of a refresh operation for the memory cell based on the soft-value or the likelihood value.

Abstract: A decoder is configured to include an acquisition-unit configured to acquire first respective likelihoods of data-bits and second respective likelihoods of parity-bits, the data-bits and the parity-bits included in code data obtained by LDPC-encoding the data-bits with a low density parity check matrix, a detecting-unit configured to detect reliabilities of the first respective likelihoods and the second respective likelihoods, a forming-unit configured to form an update schedule representing an order of updating the first and second respective likelihoods in order of increasing reliability, in accordance with the reliabilities, an updating-unit configured to update the first and second respective likelihoods in the order represented by the update schedule, with the low density parity check matrix, a discriminating-unit configured to execute hard decision of the likelihoods updated by the updating-unit, and a checking-unit configured to execute parity check of a discrimination result of the discriminating-uni

Abstract: A receiving-apparatus which includes space-filtering-unit configured to separate receive-signals into signal of first-data-sequence and signal of second-data-sequence on basis of estimation result, provisional-decoding-unit configured to LDPC-decode the two corresponding signals, to obtain provisional-likelihood-ratio for the two sequences, provisional-output-unit configured to output two provisional corresponding sequences on the basis of the respective provisional-likelihood-ratio, replica-signal-generation-unit, estimation-result of propagation-path-estimation-unit, soft-decision-outputting-unit configured to obtain receive-likelihood-values of the two sequences, on basis of residual-signal obtained by subtracting replica-signal from receive-signals, actual-decoding-unit configured to LDPC-decode receive-likelihood-values, to obtain likelihood-ratio of the two sequences, and actual-output-unit configured to obtain the two sequences on the basis of likelihood-ratio of the two sequences to hard-decision.

Abstract: Before data is transmitted from a plurality of antennas, a plurality of known symbol sequences are transmitted from these antennas. Each known symbol sequence contains a plurality of known symbols having different subcarrier arrangements. Known symbols transmitted from different antennas have different subcarrier arrangements.