Abstract: In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.

Abstract: A memory controller 2 of a memory system 1 according to an embodiment is provided with an encoding device 10 and a memory interface 5. The encoding device 10 is provided with an encoder 15 which generates a plurality of first parities by encoding a plurality of user data by using a common code, an interleaver 111 which sequentially interleaves the plurality of user data, and an XOR accumulator 112 which sequentially executes component-wise modulo-2 operation on the interleaved plurality of user data. The encoder 15 generates second parity by encoding a result finally obtained by executing the component-wise modulo-2 operation on a plurality of user data. The memory interface 5 writes a code word sequence including the plurality of user data, the first parities and the second parity in a non-volatile memory 9.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: According to an embodiment, a memory system includes: a non-volatile memory; an encoding unit that generates a code word in which zero and one occur at different occurrence rates by encoding data; and a control unit that writes k third data items and fourth data items into the non-volatile memory. The k is an integer larger than or equal to zero and smaller than or equal to n. The n is an integer larger than or equal to two. The k third data items are obtained by encoding k second data items with the encoding unit among first data items including n second data items and having a first data length. The fourth data items are obtained by removing data corresponding to the k third data items from the first data items. The third data items are generated by encoding the second data items with encoders, respectively.

Abstract: According to one embodiment, a controller controls a nonvolatile memory stores data page by page. The controller is configured to extract, from a first data sequence shorter than the data length of a page, a second data sequence shorter than the first data sequence, to refer to the difference between threshold voltages corresponding to two data included in the second data sequence, to convert the second data sequence into a third data sequence longer than the second data sequence, and to control the percentage of the length of an error correction code added to the third data sequence.

Abstract: According to one embodiment, a controller controls a nonvolatile memory stores data page by page. The controller is configured to extract, from a first data sequence shorter than the data length of a page, a second data sequence shorter than the first data sequence, to refer to the difference between threshold voltages corresponding to two data included in the second data sequence, to convert the second data sequence into a third data sequence longer than the second data sequence, and to control the percentage of the length of an error correction code added to the third data sequence.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: According to one embodiment, an encoding apparatus includes an encoding unit. The encoding unit encodes a data bit sequence to generate a codeword corresponding to a parity check matrix. The parity check matrix is based on a protograph. In the protograph, each of n check nodes of a first type is connected to n variable nodes of a first type by a total of at least one edge of a first type, and to n variable nodes of a second type by a total of at least two edges of a second type. In the protograph, each of n check nodes of a second type is connected to the n variable nodes of the second type by a total of r edges of a third type, and to n variable nodes of a third type by a total of g edges of a fourth type.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: In a network storage device that includes a plurality of data storage drives, error correction and/or recovery of data stored on one of the plurality of data storage drives is performed cooperatively by the drive itself and by a storage host that is configured to manage storage in the plurality of data storage drives. When an error-correcting code (ECC) operation performed by the drive cannot correct corrupted data stored on the drive, the storage host can attempt to correct the corrupted data based on parity and user data stored on the remaining data storage drives. In some embodiments, data correction can be performed iteratively between the drive and the storage host. Furthermore, the storage host can control latency associated with error correction by selecting a particular error correction process.

Abstract: According to an embodiment, in a parity check matrix creation method, all N column vectors in the mask matrix are different. A submatrix having M rows×L columns obtained by arbitrarily extracting L continuous columns from the mask matrix includes B1 first correction rows and Bi ith correction rows. The B1 first correction rows have at least one “1” in total in each of A1 first correction columns. Each of the Bi ith correction rows has at least one “1” in total in Ai?1 (i?1)th correction columns and has “1” in one of Ai ith correction columns included in a column set excluding the first correction columns to (i?1)th correction columns. The Bi ith correction rows include at least one “1” in total in each of the Ai ith correction columns. A sum from A1 to AI equals L.

Abstract: According to one embodiment, a controller includes a generator and a creator. The generator generates a channel matrix by counting a number of times a combination of a correct bit value and a read level appears for each bit forming a decoded first frame, based on readout data indicating a read level of each of a plurality of bits forming a frame and the decoded frame. The creator creates a table by statistically calculating a likelihood of a correct bit value of each read level based on the channel matrix.

Abstract: According to an embodiment, an error correction decoder includes a first calculation circuit and a second calculation circuit. The first calculation circuit and the second calculation circuit perform the column processing based on the second reliability information corresponding to variable nodes belonging to each of one or more valid blocks arranged in a first row group and the row processing based on the first reliability information corresponding to variable nodes belonging to one or more valid blocks arranged in a second row group whose processing order is later than that of the first row group in parallel.

Abstract: According to one embodiment, a decoding apparatus includes first and second acquisition units, a holding unit, a calculation unit, and a decision unit. The first acquisition unit acquires first measurement values of measurements performed to measure an eigenvalue of an encoded Z operator to a first encoded qubit of the two encoded qubits. The second acquisition unit acquires second measurement values of measurements performed to measure an eigenvalue of an encoded X operator to a second encoded qubit of the two encoded qubits. The holding unit holds error probabilities for the first measurement values and the second measurement values. The calculation unit calculates probabilities for measurement values of an encoded Bell measurement by using the first measurement values, the second measurement values, and the error probabilities. The decision unit decides measurement values of the encoded Bell measurement, based on the calculated probabilities.

Abstract: According to one embodiment, an error correction decoder includes a selecting section, calculating section, check section, and updating section. The selecting section selects data used for matrix processing applied to a process target row from LLR data stored in the first memory section based on a check matrix, and stores the data in a second memory section. The calculating section executes the matrix processing based on the data stored in the second memory section, and writes updated data back to the second memory section. The check section checks a parity based on a calculating result of the calculating section. The updating section updates the LLR data of the first memory section based on the updated data of the second memory section.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: According to one embodiment, an encoding apparatus includes an input unit and a generation unit. The input unit inputs a data symbol sequence containing q(N?J) symbols (q, J, and N are integers, N>J). The generation unit generates a codeword containing qN symbols by adding a parity symbol sequence containing qJ symbols to the data symbol sequence. The codeword satisfies parity check equations of a parity check matrix of qJ rows×qN columns. A first submatrix of qJ rows×qJ columns that corresponds to the parity symbol sequence in the parity check matrix includes a second submatrix. The second submatrix includes a first identity matrix of qL rows×qL columns (L is an integer, J>L) and a first non-zero matrix of q(J?L) rows×qL columns.

Abstract: A semiconductor memory device includes a plurality of detecting code generators configured to generate a plurality of detecting codes to detect errors in a plurality of data items, respectively, a plurality of first correcting code generators configured to generate a plurality of first correcting codes to correct errors in a plurality of first data blocks, respectively, each of the first data blocks containing one of the data items and a corresponding detecting code, a second correcting code generators configured to generate a second correcting code to correct errors in a second data block, the second data block containing the first data blocks, and a semiconductor memory configured to nonvolatilely store the second data block, the first correcting codes, and the second correcting code.

Abstract: According to an embodiment, in a parity check matrix creation method, all N column vectors in the mask matrix are different. A submatrix having M rows×L columns obtained by arbitrarily extracting L continuous columns from the mask matrix includes B1 first correction rows and Bi ith correction rows. The B1 first correction rows have at least one “1” in total in each of A1 first correction columns. Each of the Bi ith correction rows has at least one “1” in total in Ai-1 (i?1)th correction columns and has “1” in one of Ai ith correction columns included in a column set excluding the first correction columns to (i?1)th correction columns. The Bi ith correction rows include at least one “1” in total in each of the Ai ith correction columns. A sum from A1 to AI equals L.

Abstract: According to one embodiment, a decoder includes a control unit and a decoding unit. The control unit determines a window size applied to a first target frame to be a first value and determines a window size applied to a second target frame different from the first target frame to be a second value different from the first value. The decoding unit carries out windowed decoding of a spatially coupled code on the first target frame with the window size set to the first value and carries out windowed decoding of a spatially coupled code on the second target frame with the window size set to the second value.