Patents by Inventor Hironori Wakana

Hironori Wakana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8314032
    Abstract: A method for manufacturing a thin film transistor (TFT) through a process including back exposure, in which oxide semiconductor is used for a channel layer; using an electrode over a substrate as a mask, negative resist is exposed to light from the back of the substrate; the negative resist except its exposed part is removed; and an electrode is shaped by etching a conductive film using the exposed part as an etching mask.
    Type: Grant
    Filed: July 17, 2010
    Date of Patent: November 20, 2012
    Assignee: Hitachi, Ltd.
    Inventors: Tetsufumi Kawamura, Hiroyuki Uchiyama, Hironori Wakana, Mutsuko Hatano, Takeshi Sato
  • Publication number: 20120280227
    Abstract: Features are forming a gate electrode on an insulating substrate; forming a first semiconducting layer mainly composed of an indium oxide and having a film thickness of 5 nm or more onto the gate electrode interposing a gate insulating film; forming a second semiconducting layer mainly composed of zinc and tin oxides without containing indium and having a film thickness of 5 to 50 nm on the first semiconducting layer, and including a step of forming a source electrode and a drain electrode on the second semiconducting layer. In this manner, by combining the materials of the first semiconducting layer and the second semiconducting layer with each other, a semiconductor device with a reduced dependency on the film thickness of the semiconducting layer, little characteristic variations on a large area substrate is provided.
    Type: Application
    Filed: November 22, 2010
    Publication date: November 8, 2012
    Inventors: Hironori Wakana, Tetsufumi Kawamura, Hiroyuki Uchiyama, Kuniharu Fujii
  • Publication number: 20120025148
    Abstract: A technique capable of forming an oxide semiconductor target with a high quality in a low cost is provided. In a step of manufacturing zinc tin oxide (ZTO target) used in manufacturing an oxide semiconductor forming a channel layer of a thin-film transistor, by purposely adding the group IV element (C, Si, or Ge) or the group V element (N, P, or As) to a raw material, excessive carriers caused by the group III element (Al) mixed in the step of manufacturing the ZTO target are suppressed, and a thin-film transistor having good current (Id)-voltage (Vg) characteristics is achieved.
    Type: Application
    Filed: March 16, 2011
    Publication date: February 2, 2012
    Inventors: Hiroyuki Uchiyama, Hironori Wakana
  • Publication number: 20120012818
    Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer, and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.
    Type: Application
    Filed: August 31, 2011
    Publication date: January 19, 2012
    Inventors: Hironori WAKANA, Seiji Adachi, Koji Tsubone, Keiichi Tanabe
  • Patent number: 8032196
    Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where in cations within the material forming the barrier layer, a Cu content is in a range of 35 At. % to 55 At. % and an RE content is in a range of 12 At. % to 30 At. %, and the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.
    Type: Grant
    Filed: August 23, 2007
    Date of Patent: October 4, 2011
    Assignees: Chugoku Electric Power Co., Inc., International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Hironori Wakana, Seiji Adachi, Koji Tsubone, Keiichi Tanabe
  • Patent number: 7968368
    Abstract: A method of manufacturing a field effect transistor, which has high alignment accuracy between a gate electrode and source and drain electrodes and can provide a transparent device at a low cost. Since a patterned light blocking film is formed on the rear side of a substrate and used as a photomask for forming a gate electrode pattern and a source and drain electrode pattern on the front side of the substrate, the number of photomasks is reduced, and self-alignment between the gate electrode and the source and drain electrodes is carried out, thereby improving the alignment accuracy of these electrodes. Thereby, a method of manufacturing a high-accuracy low-cost field effect transistor can be provided.
    Type: Grant
    Filed: January 28, 2010
    Date of Patent: June 28, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Hironori Wakana, Hiroyuki Uchiyama, Tetsufumi Kawamura, Shinichi Saito
  • Publication number: 20110049508
    Abstract: In a manufacturing method for thin film transistors, the following procedure is taken: a sacrifice layer comprised of a metal oxide semiconductor is formed over a conductive layer comprised of a metal oxide semiconductor; a metal film is formed over the sacrifice layer; the metal film is processed by dry etching; and the portion of the sacrifice layer exposed by this dry etching is subjected to wet etching.
    Type: Application
    Filed: July 27, 2010
    Publication date: March 3, 2011
    Inventors: Tetsufumi KAWAMURA, Hiroyuki Uchiyama, Hironori Wakana, Mutsuko Hatano
  • Publication number: 20110042667
    Abstract: A method for manufacturing a thin film transistor (TFT) through a process including back exposure, in which oxide semiconductor is used for a channel layer; using an electrode over a substrate as a mask, negative resist is exposed to light from the back of the substrate; the negative resist except its exposed part is removed; and an electrode is shaped by etching a conductive film using the exposed part as an etching mask.
    Type: Application
    Filed: July 17, 2010
    Publication date: February 24, 2011
    Inventors: Tetsufumi KAWAMURA, Hiroyuki Uchiyama, Hironori Wakana, Mutsuko Hatano, Takeshi Sato
  • Publication number: 20100330738
    Abstract: An oxide semiconductor target of a ZTO (zinc tin complex oxide) type oxide semiconductor material of an appropriate (Zn/(Zn+Sn)) composition having high mobility and threshold potential stability and with less restriction in view of the cost and the resource and with less restriction in view of the process, and an oxide semiconductor device using the same, in which a sintered Zn tin complex oxide with a (Zn/(Zn+Sn)) composition of 0.6 to 0.8 is used as a target, the resistivity of the target itself is at a high resistance of 1 ?cm or higher and, further, the total concentration of impurities is controlled to 100 ppm or less.
    Type: Application
    Filed: April 9, 2010
    Publication date: December 30, 2010
    Inventors: Hiroyuki Uchiyama, Hironori Wakana, Tetsufumi Kawamura, Fumi Kurita, Hideko Fukushima
  • Publication number: 20100210070
    Abstract: A method of manufacturing a field effect transistor, which has high alignment accuracy between a gate electrode and source and drain electrodes and can provide a transparent device at a low cost. Since a patterned light blocking film is formed on the rear side of a substrate and used as a photomask for forming a gate electrode pattern and a source and drain electrode pattern on the front side of the substrate, the number of photomasks is reduced, and self-alignment between the gate electrode and the source and drain electrodes is carried out, thereby improving the alignment accuracy of these electrodes. Thereby, a method of manufacturing a high-accuracy low-cost field effect transistor can be provided.
    Type: Application
    Filed: January 28, 2010
    Publication date: August 19, 2010
    Inventors: HIRONORI WAKANA, Hiroyuki UCHIYAMA, Tetsufumi KAWAMURA, Shinichi SAITO
  • Publication number: 20100140614
    Abstract: A phenomenon of change of a contact resistance between an oxide semiconductor and a metal depending on an oxygen content ratio in introduced gas upon depositing an oxide semiconductor film made of indium gallium zinc oxide, zinc tin oxide, or others in an oxide semiconductor thin-film transistor. A contact layer is formed with an oxygen content ratio of 10% or higher in a region from a surface, where the metal and the oxide semiconductor are contacted, down to at least 3 nm deep in depth direction, and a region to be a main channel layer is further formed with an oxygen content ratio of 10% or lower, so that a multilayered structure is formed, and both of ohmic characteristics to the electrode metal and reliability such as the suppression of threshold potential shift are achieved.
    Type: Application
    Filed: December 8, 2009
    Publication date: June 10, 2010
    Inventors: Hiroyuki Uchiyama, Tetsufumi Kawamura, Hironori Wakana
  • Publication number: 20100006825
    Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.
    Type: Application
    Filed: August 28, 2009
    Publication date: January 14, 2010
    Inventors: Hironori WAKANA, Koji TSUBONE, Yoshinobu TARUTANI, Yoshihiro ISHIMARU, Keiichi TANABE
  • Publication number: 20080051292
    Abstract: A Josephson device includes a first superconducting electrode layer, a barrier layer and a second superconducting electrode layer that are successively stacked. The first and second superconducting electrode layers are made of an oxide superconductor material having (RE)1(AE)2Cu3Oy as a main component, where an element RE is at least one element selected from a group consisting of Y, La, Pr, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, and an element AE is at least one element selected from a group consisting of Ba, Sr and Ca. The barrier layer is made of a material that includes the element RE, the element AE, Cu and oxygen, where in cations within the material forming the barrier layer, a Cu content is in a range of 35 At. % to 55 At. % and an RE content is in a range of 12 At. % to 30 At. %, and the barrier layer has a composition different from compositions of the first and second superconducting electrode layers.
    Type: Application
    Filed: August 23, 2007
    Publication date: February 28, 2008
    Inventors: Hironori Wakana, Seiji Adachi, Koji Tsubone, Keiichi Tanabe
  • Publication number: 20070158791
    Abstract: A superconducting junction element has a lower electrode formed by a superconductor layer, a barrier layer provided on a portion of a surface of the lower electrode, an upper electrode formed by a superconductor and covering the barrier layer, and a superconducting junction formed by the lower electrode, the barrier layer and the upper electrode. A critical current density of the superconducting junction is controlled based on an area of the lower electrode.
    Type: Application
    Filed: October 20, 2006
    Publication date: July 12, 2007
    Inventors: Hironori Wakana, Koji Tsubone, Yoshinobu Tarutani, Yoshihiro Ishimaru, Keiichi Tanabe
  • Publication number: 20060247131
    Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.
    Type: Application
    Filed: January 13, 2006
    Publication date: November 2, 2006
    Applicants: FUJITSU LIMITED, INTERNATIONAL SUPERCONDUCTIVITY TECHNOLOGY CENTER, THE JURIDICAL FOUNDATION
    Inventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
  • Patent number: 7091515
    Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.
    Type: Grant
    Filed: March 26, 2004
    Date of Patent: August 15, 2006
    Assignees: Fujitsu Limited, International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
  • Patent number: 6999806
    Abstract: A Josephson junction having a barrier layer sandwiched by two superconductors wherein the superconductors include one or more elements selected from the group of Y, La, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, one or more elements selected from the group of Ba, Sr and Ca, and Cu and oxygen, wherein the two superconductors each include at least five elements with compositions different from each other, or the barrier layer (5) includes one or more elements selected from the group of La, Nd, Sm and Eu, and one or more elements selected from the group of Y, Gd, Dy, Ho, Er, Tm, Yb and Lu.
    Type: Grant
    Filed: August 16, 2002
    Date of Patent: February 14, 2006
    Assignee: International Superconductivity Technology Center, the Juridical Foundation
    Inventors: Seiji Adachi, Hironori Wakana, Keiichi Tanabe
  • Publication number: 20040232405
    Abstract: At least two ramp-edge-structure Josephson junctions having different critical current densities to one another are provided on a substrate.
    Type: Application
    Filed: March 26, 2004
    Publication date: November 25, 2004
    Inventors: Masahiro Horibe, Hideo Suzuki, Yoshihiro Ishimaru, Hironori Wakana, Keiichi Tanabe
  • Patent number: 6790675
    Abstract: A method of fabricating a Josephson device includes the steps of forming a first superconducting layer and forming a second superconducting layer to form a Josephson junction therebetween, wherein the step of forming the second superconducting layer includes the steps of conducting a first step of forming the second superconducting layer with improved uniformity and conducting a second step of forming the second superconducting layer on the second superconducting layer formed in the first step with improved film quality.
    Type: Grant
    Filed: March 18, 2003
    Date of Patent: September 14, 2004
    Assignees: International Superconductivity Technology Center, The Juridical Foundation
    Inventors: Seiji Adachi, Hironori Wakana, Yoshihiro Ishimaru, Masahiro Horibe, Osami Horibe, Yoshinobu Tarutani, Keiichi Tanabe
  • Publication number: 20040077504
    Abstract: A Josephson junction having a barrier layer sandwiched by two superconductors wherein the superconductors include one or more elements selected from the group of Y, La, Nd, Sm, Eu, Gd, Dy, Ho, Er, Tm, Yb and Lu, one or more elements selected from the group of Ba, Sr and Ca, and Cu and oxygen, wherein the two superconductors each include at least five elements with compositions different from each other, or the barrier layer (5) includes one or more elements selected from the group of La, Nd, Sm and Eu, and one or more elements selected from the group of Y, Gd, Dy, Ho, Er, Tm, Yb and Lu.
    Type: Application
    Filed: July 10, 2003
    Publication date: April 22, 2004
    Inventors: Seiji Adachi, Hironori Wakana, Keiichi Tanabe