Abstract: A radiation measuring apparatus (20) includes a scatterer detector (10A), an absorber detector (10B) and a processing unit (12). Pixel electrodes (2) of the scatterer detector (10A) and the absorber detector (10B) are arranged such that a distance between centers of two neighbor pixel electrodes (2) is smaller than a mean free path of a recoil electron generated in the Compton scattering of an electromagnetic radiation. The processing unit (12) specifies and incidence direction of the electromagnetic radiation based on a recoiling direction to which the recoil electron recoils. In this way, an electron tracking-type Compton camera is realized which confines the incidence direction of the electromagnetic radiation by using the recoiling direction of the recoil electron in a Compton camera using a semiconductor detector.

Abstract: In a signal processing device of an embodiment, an integration circuit accumulates a charge from a photodiode in an integrating capacitor element, and outputs a voltage value according to the amount of charge. A comparator circuit, when the voltage value from the integration circuit has reached a reference value, outputs a saturation signal. A charge injection circuit, in response to the saturation signal, injects an opposite polarity of charge into the integrating capacitor element. A counter circuit performs counting based on the saturation signal. A holding circuit holds the voltage value from the integration circuit. An amplifier circuit outputs a voltage value that is K times (where K>1) larger than the voltage value held by the holding circuit. An A/D converter circuit sets a voltage value that is K times larger than the reference value as the maximum input voltage value, that is, a full-scale value, and outputs a digital value corresponding to the voltage value from the amplifier circuit.

Abstract: A semiconductor integrated circuit which operates based on a power supply voltage output from a power supply device configured to generate a voltage of a magnitude in accordance with an analog control signal includes: a first terminal to which the power supply voltage is applied; an internal interconnect which is connected to the first terminal, and distributes the power supply voltage to sections in the semiconductor integrated circuit; and a second terminal from which the analog control signal is output. The analog control signal is generated to have a magnitude in accordance with a potential of the internal interconnect.

Abstract: In a semiconductor device, a resistance divider includes a first resistor connecting a supply line to an output node of an analog control signal, a second resistor connecting an output node to ground, a first switching device that is turned on or off by a control circuit, and a second switching device that turns on in response to a voltage equal to the voltage of the supply line. The control circuit turns on the first switching device until a power supply voltage reaches a predetermined voltage, and then turns on or off the first switching device.

Abstract: A power supply potential detecting circuit detects a power supply potential of a second circuit block when a first circuit block shifts from a power supply shutdown state to a power supply feeding state or shifts from the power supply feeding state to the power supply shutdown state. Then, an operation control circuit temporarily stops a function of the second circuit block when the first circuit block shifts from the power supply shutdown state to the power supply feeding state or shifts from the power supply feeding state to the power supply shutdown state and then recovers the function of the second circuit block based on a detection result outputted from the power supply potential detecting circuit.

Abstract: A control circuit receives a change request for an operating mode of a signal processor which operates based on an output voltage of a regulator circuit, changes the output voltage of the regulator circuit, and then changes the operating mode of the signal processor based on the change request.

Abstract: In a signal processing device of an embodiment, an integration circuit accumulates a charge from a photodiode in an integrating capacitor element, and outputs a voltage value according to the amount of charge. A comparator circuit, when the voltage value from the integration circuit has reached a reference value, outputs a saturation signal. A charge injection circuit, in response to the saturation signal, injects an opposite polarity of charge into the integrating capacitor element. A counter circuit performs counting based on the saturation signal. A holding circuit holds the voltage value from the integration circuit. An amplifier circuit outputs a voltage value that is K times (where K>1) larger than the voltage value held by the holding circuit. An A/D converter circuit sets a voltage value that is K times larger than the reference value as the maximum input voltage value, that is, a full-scale value, and outputs a digital value corresponding to the voltage value from the amplifier circuit.

Abstract: A photodetecting device 1 includes a photodiode PDm,n, a switch SWm,n for the photodiode, an integrating circuit 12m, and a noise removing circuit 13m. The integrating circuit 12m accumulates in a capacitor Cfk an electric charge input from the photodiode PDm,n through the switch SWm,n for the photodiode, and outputs a voltage value according to the amount of the accumulated electric charge. The noise removing circuit 13m includes an amplifier A3, five switches SW31 to SW35, four capacitors C31 to C34, and a power supply V3. The noise removing circuit 13m takes in a voltage value that is output from the integrating circuit 12m at a time where the switch SW31 is first turned from a closed state to an open state, and after the time, outputs a voltage value according to a difference between the voltage value that is output from the integrating circuit 12m and the voltage value previously taken in.

Abstract: An amount of charges consonant with the intensity of the light entering photodiodes is generated, and the level of the charges is determined by a charge level determination circuit. Based on this determined charge level, a capacitance setting circuit sets a capacitance of an integrating capacitor unit in an integrating circuit. Thereafter, in the integrating circuit, the charges generated by the photodiodes are integrated in the integrating capacitor unit, and a voltage having a value consonant with the amount of the integrated charges is output. When background light is strong and the overall intensity of incident light is high, a comparatively large capacitance is set for the variable capacitor unit of the integrating circuit, and the intensity of the incident light is detected without saturation.

Abstract: The A/D converting circuit 20 is provided with a differential amplifying portion 21, a first variable capacitance portion 22A, a second variable capacitance portion 22B, a comparing portion 23, a connection controlling portion 24, a first feedback portion 25A and a second feedback portion 25B. Voltage values output as a differential signal from the first output terminal and the second output terminal of the differential amplifying portion 21 are converted to 6-bit digital values by a successive approximation type A/D converting circuit (made up of a first variable capacitance portion 22A, a second variable capacitance portion 22B, a comparing portion 23 and a connection controlling portion 24) and output.

Abstract: A photodetector includes a plurality of photodetecting elements which output electrical signals corresponding to the intensities of light that entered these; a signal processing element which is opposed to the photodetecting elements and is connected to the photodetecting elements via conductive bumps, and into which electrical signals output from the photodetecting elements are input; a resin which has electrical insulation and is filled in at least at the gaps between the photodetecting elements and the signal processing element; and a light shielding member arranged so as to cover the surfaces exposed from the photodetecting elements and the signal processing element in the resin.

Abstract: The A/D converting circuit 20 is provided with a differential amplifying portion 21, a first variable capacitance portion 22A, a second variable capacitance portion 22B, a comparing portion 23, a connection controlling portion 24, a first feedback portion 25A and a second feedback portion 25B. Voltage values output as a differential signal from the first output terminal and the second output terminal of the differential amplifying portion 21 are converted to 6-bit digital values by a successive approximation type A/D converting circuit (made up of a first variable capacitance portion 22A, a second variable capacitance portion 22B, a comparing portion 23 and a connection controlling portion 24) and output.

Abstract: A power supply potential detecting circuit detects a power supply potential of a second circuit block when a first circuit block shifts from a power supply shutdown state to a power supply feeding state or shifts from the power supply feeding state to the power supply shutdown state. Then, an operation control circuit temporarily stops a function of the second circuit block when the first circuit block shifts from the power supply shutdown state to the power supply feeding state or shifts from the power supply feeding state to the power supply shutdown state and then recovers the function of the second circuit block based on a detection result outputted from the power supply potential detecting circuit.

Abstract: A photodetecting device 1 includes a photodiode PDm,n, a switch SWm,n for the photodiode, an integrating circuit 12m, and a noise removing circuit 13m. The integrating circuit 12m accumulates in a capacitor Cfk an electric charge input from the photodiode PDm,n through the switch SWm,n for the photodiode, and outputs a voltage value according to the amount of the accumulated electric charge. The noise removing circuit 13m includes an amplifier A3, five switches SW31 to SW35, four capacitors C31 to C34, and a power supply V3. The noise removing circuit 13m takes in a voltage value that is output from the integrating circuit 12m at a time where the switch SW31 is first turned from a closed state to an open state, and after the time, outputs a voltage value according to a difference between the voltage value that is output from the integrating circuit 12m and the voltage value previously taken in.

Abstract: A photodetector includes a plurality of photodetecting elements which output electrical signals corresponding to the intensities of light that entered these; a signal processing element which is opposed to the photodetecting elements and is connected to the photodetecting elements via conductive bumps, and into which electrical signals output from the photodetecting elements are input; a resin which has electrical insulation and is filled in at least at the gaps between the photodetecting elements and the signal processing element; and a light shielding member arranged so as to cover the surfaces exposed from the photodetecting elements and the signal processing element in the resin.

Abstract: An amount of charges consonant with the intensity of the light entering photodiodes is generated, and the level of the charges is determined by a charge level determination circuit. Based on this determined charge level, a capacitance setting circuit sets a capacitance of an integrating capacitor unit in an integrating circuit. Thereafter, in the integrating circuit, the charges generated by the photodiodes are integrated in the integrating capacitor unit, and a voltage having a value consonant with the amount of the integrated charges is output. When background light is strong and the overall intensity of incident light is high, a comparatively large capacitance is set for the variable capacitor unit of the integrating circuit, and the intensity of the incident light is detected without saturation.

Abstract: An amount of charges consonant with the intensity of the light entering photodiodes is generated, and the level of the charges is determined by a charge level determination circuit. Based on this determined charge level, a capacitance setting circuit sets a capacitance of an integrating capacitor unit in an integrating circuit. Thereafter, in the integrating circuit, the charges generated by the photodiodes are integrated in the integrating capacitor unit, and a voltage having a value consonant with the amount of the integrated charges is output. When background light is strong and the overall intensity of incident light is high, a comparatively large capacitance is set for the variable capacitor unit of the integrating circuit, and the intensity of the incident light is detected without saturation.

Abstract: In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit.

Abstract: It is an object of the present invention to achieve a semiconductor device capable of preventing circuit malfunctions caused by noise without decreasing an integration degree of the circuit by making a space between signal interconnections wider and inserting a shield or a shield layer between the signal interconnections. The semiconductor device has a multilayer interconnection structure wherein three or more interconnection layers are stacked on a silicon semiconductor substrate, and comprises: a first signal line which is formed with a (N?1)-th interconnection layer and comprises a latch circuit; a second signal line which is formed with a (N+1)-th interconnection layer and is arranged so as to cross the first signal line or partially overlap thereover; and a power supply interconnection serving as a shield interconnection which is formed with an N-th interconnection layer in a portion directly beneath the first signal line and the second signal line.

Abstract: In a level shifter, in the case where the amplitude voltage of an input signal (i.e., a first power voltage VDDL) input to an input terminal is changed to be higher and the amplitude voltage of an output signal (i.e., a second power voltage VDDH) output from an output terminal is changed to be lower, a fall delay time of the signal output from the output terminal tends to be longer than a rise delay time of the signal. However, an inverted input signal obtained by an inverter is input to a level shifting unit and also to the gate of an N-type transistor, and therefore, the N-type transistor is turned on at the fall of the input signal input to the input terminal, so as to supply a current based on the second power voltage VDDH to an output node of the level shifting unit for assisting the shift into H level performed in the level shifting unit.