Patents by Inventor Hirosato Ochimizu
Hirosato Ochimizu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11488913Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.Type: GrantFiled: September 29, 2020Date of Patent: November 1, 2022Assignee: Socionext Inc.Inventors: Akio Hara, Toyoji Sawada, Masaki Okuno, Hirosato Ochimizu
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Publication number: 20210028129Abstract: A semiconductor device includes a substrate having a circuit region and a peripheral region disposed around and enclosing the circuit region in a plan view, a first interconnect layer formed on the substrate, a second interconnect layer formed on the first interconnect layer, a third interconnect layer formed on the second interconnect layer, and a guard ring formed in the peripheral region, wherein the guard ring includes a first interconnect formed in the first interconnect layer, and disposed around and enclosing the circuit region in a plan view, a second interconnect formed in the third interconnect layer, and disposed around and enclosing the circuit region in a plan view, and a first via connected to the first interconnect and to the second interconnect, and disposed in a groove shape along a perimeter edge of the substrate in a plan view.Type: ApplicationFiled: September 29, 2020Publication date: January 28, 2021Inventors: Akio HARA, Toyoji SAWADA, Masaki OKUNO, Hirosato OCHIMIZU
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Patent number: 9704740Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.Type: GrantFiled: October 27, 2016Date of Patent: July 11, 2017Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hirosato Ochimizu, Atsuhiro Tsukune, Hiroshi Kudo
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Publication number: 20170047246Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.Type: ApplicationFiled: October 27, 2016Publication date: February 16, 2017Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hirosato OCHIMIZU, Atsuhiro TSUKUNE, Hiroshi KUDO
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Patent number: 9236302Abstract: A semiconductor device has a semiconductor substrate having a first surface and a second surface, a through electrode penetrating through the semiconductor substrate and having a protrusion protruding from the second surface, and an insulation layer on the second surface, which covers the side surface of the protrusion, has an opening through which to expose the end surface of the protrusion, and has a thickness greater than the length of the protrusion.Type: GrantFiled: May 4, 2015Date of Patent: January 12, 2016Assignee: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hikaru Ohira, Tamotsu Owada, Hirosato Ochimizu
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Publication number: 20150235901Abstract: A semiconductor device has a semiconductor substrate having a first surface and a second surface, a through electrode penetrating through the semiconductor substrate and having a protrusion protruding from the second surface, and an insulation layer on the second surface, which covers the side surface of the protrusion, has an opening through which to expose the end surface of the protrusion, and has a thickness greater than the length of the protrusion.Type: ApplicationFiled: May 4, 2015Publication date: August 20, 2015Inventors: Hikaru Ohira, Tamotsu Owada, Hirosato Ochimizu
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Publication number: 20150069586Abstract: A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate.Type: ApplicationFiled: November 18, 2014Publication date: March 12, 2015Inventors: Tamotsu Owada, Hikaru Ohira, Hirosato Ochimizu
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Patent number: 8916468Abstract: A transistor formed on a semiconductor substrate is covered with a first insulating film, and first conductive vias which pierce the first insulating film and which reach the transistor and a second conductive via which pierces the first insulating film and which reaches an inside of the semiconductor substrate are formed. After the formation of the first conductive vias and the second conductive via, a second insulating film is formed over the first insulating film. Conducive portions connected to the first conductive vias leading to the transistor and a conductive portion connected to the second conductive via which reaches the inside of the semiconductor substrate are formed in the second insulating film. By doing so, a multilayer interconnection is formed.Type: GrantFiled: June 6, 2013Date of Patent: December 23, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Hirosato Ochimizu, Atsuhiro Tsukune
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Patent number: 8916423Abstract: A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate.Type: GrantFiled: March 8, 2013Date of Patent: December 23, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Tamotsu Owada, Hikaru Ohira, Hirosato Ochimizu
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Publication number: 20140353829Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.Type: ApplicationFiled: August 14, 2014Publication date: December 4, 2014Inventors: Hirosato OCHIMIZU, Atsuhiro TSUKUNE, Hiroshi KUDO
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Publication number: 20140306339Abstract: A semiconductor device has a semiconductor substrate having a first surface and a second surface, a through electrode penetrating through the semiconductor substrate and having a protrusion protruding from the second surface, and an insulation layer on the second surface, which covers the side surface of the protrusion, has an opening through which to expose the end surface of the protrusion, and has a thickness greater than the length of the protrusion.Type: ApplicationFiled: March 12, 2014Publication date: October 16, 2014Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Hikaru Ohira, Tamotsu Owada, Hirosato Ochimizu
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Patent number: 8836126Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.Type: GrantFiled: August 4, 2009Date of Patent: September 16, 2014Assignee: Fujitsu Semiconductor LimitedInventors: Hirosato Ochimizu, Atsuhiro Tsukune, Hiroshi Kudo
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Publication number: 20130320508Abstract: A method of manufacturing a semiconductor device includes: forming a first electrode on a first semiconductor substrate; coating the semiconductor substrate with an insulating material having a first viscosity at a first temperature, having a second viscosity lower than the first viscosity at a second temperature higher than the first temperature, and having a third viscosity higher than the second viscosity at a third temperature higher than the second temperature; and forming a first insulating film by curing the insulating material. In this method, the forming the first insulating film includes: bringing the insulating material to the second viscosity by heating the insulating material under a first condition; and bringing the insulating material to the third viscosity by heating the insulating material under a second condition. The first condition and the second condition are different in their temperature rising rate.Type: ApplicationFiled: March 8, 2013Publication date: December 5, 2013Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventors: Tamotsu Owada, Hikaru Ohira, Hirosato Ochimizu
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Publication number: 20130273701Abstract: A transistor formed on a semiconductor substrate is covered with a first insulating film, and first conductive vias which pierce the first insulating film and which reach the transistor and a second conductive via which pierces the first insulating film and which reaches an inside of the semiconductor substrate are formed. After the formation of the first conductive vias and the second conductive via, a second insulating film is formed over the first insulating film. Conducive portions connected to the first conductive vias leading to the transistor and a conductive portion connected to the second conductive via which reaches the inside of the semiconductor substrate are formed in the second insulating film. By doing so, a multilayer interconnection is formed.Type: ApplicationFiled: June 6, 2013Publication date: October 17, 2013Inventors: Hirosato Ochimizu, Atsuhiro Tsukune
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Publication number: 20100038792Abstract: A semiconductor device includes an insulating layer formed over a semiconductor substrate, the insulating layer including oxygen, a first wire formed in the insulating layer, and a second wire formed in the insulating layer over the first wire and containing manganese, oxygen, and copper, the second wire having a projection portion formed in the insulating layer and extending downwardly but spaced apart from the first wire.Type: ApplicationFiled: August 4, 2009Publication date: February 18, 2010Applicant: FUJITSU MICROELECTRONICS LIMITEDInventors: Hirosato OCHIMIZU, Atsuhiro Tsukune, Hiroshi Kudo
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Publication number: 20090039391Abstract: On an insulation layer 12 formed on a silicon substrate 10, there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34, a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34, a tensile-strained silicon layer 24 formed on the silicon germanium layer 22 and a gate electrode 28 formed on the silicon layer 24 with a gate insulation film 26 formed therebetween and in a PMOS transistor region 20 a PMOS transistor 18 comprising a silicon layer 34, a compression-strained silicon germanium layer formed on the silicon layer 34 and a gate electrode 28 formed on the silicon germanium layer 36 with a gate insulation film 26 formed therebetween.Type: ApplicationFiled: October 1, 2008Publication date: February 12, 2009Applicant: Fujitsu LimitedInventors: Hirosato Ochimizu, Yasuyoshi Mishima
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Patent number: 7449379Abstract: On an insulation layer 12 formed on a silicon substrate 10, there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34, a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34, a tensile-strained silicon layer 24 formed on the silicon germanium layer 22 and a gate electrode 28 formed on the silicon layer 24 with a gate insulation film 26 formed therebetween and in a PMOS transistor region 20 a PMOS transistor 18 comprising a silicon layer 34, a compression-strained silicon germanium layer formed on the silicon layer 34 and a gate electrode 28 formed on the silicon germanium layer 36 with a gate insulation film 26 formed therebetween.Type: GrantFiled: November 14, 2005Date of Patent: November 11, 2008Assignee: Fujitsu LimitedInventors: Hirosato Ochimizu, Yasuyoshi Mishima
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Publication number: 20060068557Abstract: On an insulation layer 12 formed on a silicon substrate 10, there are formed in an NMOS transistor region 16 an NMOS transistor 14 comprising a silicon layer 34, a lattice-relaxed silicon germanium layer 22 formed on the silicon layer 34, a tensile-strained silicon layer 24 formed on the silicon germanium layer 22 and a gate electrode 28 formed on the silicon layer 24 with a gate insulation film 26 formed therebetween and in a PMOS transistor region 20 a PMOS transistor 18 comprising a silicon layer 34, a compression-strained silicon germanium layer formed on the silicon layer 34 and a gate electrode 28 formed on the silicon germanium layer 36 with a gate insulation film 26 formed therebetween.Type: ApplicationFiled: November 14, 2005Publication date: March 30, 2006Applicant: FUJITSU LIMITEDInventors: Hirosato Ochimizu, Yasuyoshi Mishima
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Patent number: 5945690Abstract: The present invention includes a process of growing a compound semiconductor layer locally, after applying radical particles that do not become an etchant of a compound semiconductor layer to an insulating mask so as to terminate the surface of the insulating mask in a state that the compound semiconductor layer is covered with the insulating mask, on the surface of the compound semiconductor layer exposed from the insulating mask.Type: GrantFiled: February 18, 1998Date of Patent: August 31, 1999Assignee: Fujitsu LimitedInventors: Junji Saito, Toshihide Kikkawa, Hirosato Ochimizu
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Patent number: 5844303Abstract: A semiconductor device includes a buffer layer of AlGaAs that contains oxygen with a concentration level in the approximate range of 8.times.10.sup.17 cm.sup.-3 to 6.times.10.sup.19 cm.sup.-3, and carbon with a concentration level in the approximate range of 2.times.10.sup.16 cm.sup.-3 to 2.times.10.sup.17 cm.sup.-3. A lattice constant of the AlGaAs buffer layer is larger than a lattice constant of the GaAs substrate so a lattice misfit of the AlGaAs layer with respect to the GaAs substrate is equal to or varies by no more than 2.times.10.sup.5 from a corresponding lattice misfit between an undoped AlGaAs crystal with respect to the GaAs substrate. Oxygen atoms occupy an interstitial site, creating a deep impurity level that suppresses side gate effect.Type: GrantFiled: March 17, 1994Date of Patent: December 1, 1998Assignee: Fujitsu LimitedInventors: Toshihide Kikkawa, Tatsuya Ohori, Hirosato Ochimizu