Abstract: A novel antibody that can be used as an anti-tumor agent and an anti-tumor agent that comprises, as an active ingredient, a molecule containing such an antibody.

Abstract: A diagnostic device includes: a receiver that receives data of only some of battery cells constituting a storage battery system; and a controller that diagnoses the storage battery system based on the received data. The data has a voltage value and an integrated current amount value. The some of the battery cells include: a low-state MIN battery cell; a low-state MAX battery cell; a high-state MIN battery cell; and a high-state MAX battery cell. The controller executes at least one of: determining whether the battery cells are in a balanced state or an imbalance state; calculating an imbalance amount between capacities of the battery cells; or calculating a value related to a capacity of a battery cell.

Abstract: A diagnostic device includes: a calculator that calculates a value related to a capacity of a battery cell based on a result of comparison between a measurement Q-V curve and a reference Q-V curve, the measurement Q-V curve indicating a relation between a voltage and an integrated current amount that are obtained from measurement data of the battery cell. The calculator further calculates at least one of: an amount of capacity deterioration caused by a voltage difference between the measurement Q-V curve and the reference Q-V curve by multiplying an inclination of the measurement Q-V curve by the voltage difference, and a temporary maximum capacity after capacity deterioration caused by a change in the inclination of the measurement Q-V curve to an inclination of the reference Q-V curve.

Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes: forming memory cells and select transistors on a semiconductor substrate configured to select any memory cell, forming a first insulating nitride film, forming a contact, and selectively removing the first insulating nitride film. The first insulating nitride film is formed so as to cover the semiconductor substrate between the select transistors adjacent in the first direction, the select transistors, and the memory cells. The first insulating nitride film is selectively removed in a region other than the region in which the contact is formed and in a region above the select transistors or the memory cells.

Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes: forming memory cells and select transistors on a semiconductor substrate configured to select any memory cell, forming a first insulating nitride film, forming a contact, and selectively removing the first insulating nitride film. The first insulating nitride film is formed so as to cover the semiconductor substrate between the select transistors adjacent in the first direction, the select transistors, and the memory cells. The first insulating nitride film is selectively removed in a region other than the region in which the contact is formed and in a region above the select transistors or the memory cells.

Abstract: A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to improve the hydrogen termination on the wafer surface.

Abstract: According to an embodiment, a non-volatile semiconductor storage device includes a silicon substrate including an active region isolated by an element isolation insulating film, a first insulating film formed on the active region, a charge accumulation layer formed on the first insulating film, a second insulating film formed on the charge accumulation layer, and a control gate formed on the second insulating film. A plane of the active region being in contact with the element isolation insulating film is a (100) plane or a plane inclining from the (100) plane by an inclination angle of 5° or less.

Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.

Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.

Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.

Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

Abstract: A solid-state imaging apparatuses IS1 comprises a package P1, a CCD chip 11, chip resistor arrays 21, etc. In package P1, a mounting portion 2, for mounting CCD chip 11 and chip resistor arrays 21, is disposed so as to protrude into a hollow portion 1. Mounting portion 2 has a first planar portion 3 and second planar portions 4, and first planar portion 3 and second planar portions 4 are formed to be stepped with respect to each other. CCD chip 11 is mounted and fixed on first planar portion 3 via a spacer 13. Chip resistor arrays 21 are mounted and fixed on second planar portions 4. Using the step difference between first planar portion 3 and second planar portions 4, CCD chip 11 and chip resistor arrays 21 are positioned proximally.

Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.

Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.

Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film comprising a plurality of insulating films provided on the charge storage layer and comprising a nitride film as an uppermost layer, and a single-layer control gate electrode provided on the second insulating film and comprising metal silicide.

Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.

Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode.

Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a first isolation groove penetrating through a conductive film serving as the gate electrode to reach the semiconductor substrate. The method can include forming a protection film covering a side wall of the first isolation groove including a side face of the gate electrode. The method can include forming a second isolation groove by etching the semiconductor substrate exposed to a bottom surface of the first isolation groove. The method can include oxidizing an inner surface of the second isolation groove provided on each of both sides of the gate electrode to form first insulating films, which are connected to each other under the gate electrode.

Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.