Patents by Inventor Hiroshi Akahori

Hiroshi Akahori has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10369749
    Abstract: The first electrode section (7a) and the second electrode section (7b) are formed such that the outer portion connected to the upper portion of the heating section (6) is thinner than the inner portion connected to the lower portion of the heating section (6). The heating section (6) and the first electrode section (7a) are interconnected by an R-shaped first connecting portion (21). The inner circumferential sloping surface of the heating section (6) and the second electrode section (7b) are interconnected by an R-shaped second connecting portion (22). The first and second connecting portions (21)(22) are formed such that R becomes larger from the upper end to the lower end, where the upper portion is thin and the lower portion is thick. The thickness of an intermediate portion (6b) is smaller than the thicknesses of the first and second connecting portions (21)(22).
    Type: Grant
    Filed: July 12, 2018
    Date of Patent: August 6, 2019
    Assignee: HONDA MOTOR CO., LTD.
    Inventors: Yoshinori Tsurugai, Hiroshi Ishikawa, Yuichi Tajiri, Shigeto Akahori, Naohiro Ohtsu, Satoshi Shiozaki
  • Publication number: 20160071857
    Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes: forming memory cells and select transistors on a semiconductor substrate configured to select any memory cell, forming a first insulating nitride film, forming a contact, and selectively removing the first insulating nitride film. The first insulating nitride film is formed so as to cover the semiconductor substrate between the select transistors adjacent in the first direction, the select transistors, and the memory cells. The first insulating nitride film is selectively removed in a region other than the region in which the contact is formed and in a region above the select transistors or the memory cells.
    Type: Application
    Filed: March 13, 2015
    Publication date: March 10, 2016
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuhito KUGE, Hiroshi Akahori
  • Patent number: 9269718
    Abstract: In accordance with an embodiment, a manufacturing method of a semiconductor device includes: forming memory cells and select transistors on a semiconductor substrate configured to select any memory cell, forming a first insulating nitride film, forming a contact, and selectively removing the first insulating nitride film. The first insulating nitride film is formed so as to cover the semiconductor substrate between the select transistors adjacent in the first direction, the select transistors, and the memory cells. The first insulating nitride film is selectively removed in a region other than the region in which the contact is formed and in a region above the select transistors or the memory cells.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: February 23, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Nobuhito Kuge, Hiroshi Akahori
  • Patent number: 8895410
    Abstract: A cause of deteriorating the hydrogen termination on the surface of a wafer is found to be water adsorbed on the surface. By exposing the wafer to an inert gas atmosphere containing an H2 gas so as to suppress the oxidation reaction due to the water, it is possible to improve the hydrogen termination on the wafer surface.
    Type: Grant
    Filed: September 13, 2005
    Date of Patent: November 25, 2014
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Akahori
  • Publication number: 20140239366
    Abstract: According to an embodiment, a non-volatile semiconductor storage device includes a silicon substrate including an active region isolated by an element isolation insulating film, a first insulating film formed on the active region, a charge accumulation layer formed on the first insulating film, a second insulating film formed on the charge accumulation layer, and a control gate formed on the second insulating film. A plane of the active region being in contact with the element isolation insulating film is a (100) plane or a plane inclining from the (100) plane by an inclination angle of 5° or less.
    Type: Application
    Filed: February 21, 2014
    Publication date: August 28, 2014
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventors: Takashi IZUMIDA, Masaki KONDO, Hiroshi AKAHORI, Nobutoshi AOKI
  • Patent number: 8723245
    Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.
    Type: Grant
    Filed: March 21, 2011
    Date of Patent: May 13, 2014
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Akahori, Kiyohito Nishihara, Masaki Kondo, Yingkang Zhang, Shigeo Kondo, Hidenobu Nagashima, Kazuaki Iwasawa, Takashi Ichikawa
  • Patent number: 8450787
    Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.
    Type: Grant
    Filed: October 20, 2011
    Date of Patent: May 28, 2013
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Akahori, Wakako Takeuchi
  • Patent number: 8330206
    Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
    Type: Grant
    Filed: February 14, 2012
    Date of Patent: December 11, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Akahori, Wakako Takeuchi, Atsuhiro Sato
  • Publication number: 20120208375
    Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
    Type: Application
    Filed: April 23, 2012
    Publication date: August 16, 2012
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii
  • Patent number: 8243175
    Abstract: A solid-state imaging apparatuses IS1 comprises a package P1, a CCD chip 11, chip resistor arrays 21, etc. In package P1, a mounting portion 2, for mounting CCD chip 11 and chip resistor arrays 21, is disposed so as to protrude into a hollow portion 1. Mounting portion 2 has a first planar portion 3 and second planar portions 4, and first planar portion 3 and second planar portions 4 are formed to be stepped with respect to each other. CCD chip 11 is mounted and fixed on first planar portion 3 via a spacer 13. Chip resistor arrays 21 are mounted and fixed on second planar portions 4. Using the step difference between first planar portion 3 and second planar portions 4, CCD chip 11 and chip resistor arrays 21 are positioned proximally.
    Type: Grant
    Filed: April 14, 2004
    Date of Patent: August 14, 2012
    Assignee: Hamamatsu Photonics K.K.
    Inventors: Hiroya Kobayashi, Hiroshi Akahori, Masaharu Muramatsu
  • Publication number: 20120139032
    Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
    Type: Application
    Filed: February 14, 2012
    Publication date: June 7, 2012
    Inventors: Hiroshi AKAHORI, Wakako Takeuchi, Atsuhiro Sato
  • Patent number: 8183670
    Abstract: In a semiconductor device formed on a silicon surface which has a substantial (110) crystal plane orientation, the silicon surface is flattened so that an arithmetical mean deviation of surface Ra is not greater than 0.15 nm, preferably, 0.09 nm, which enables to manufacture an n-MOS transistor of a high mobility. Such a flattened silicon surface is obtained by repeating a deposition process of a self-sacrifice oxide film in an oxygen radical atmosphere and a removing process of the self-sacrifice oxide film, by cleaning the silicon surface in deaerated H2O or a low OH density atmosphere, or by strongly terminating the silicon surface by hydrogen or heavy hydrogen. The deposition process of the self-sacrifice oxide film may be carried out by isotropic oxidation.
    Type: Grant
    Filed: January 9, 2007
    Date of Patent: May 22, 2012
    Assignee: Foundation for Advancement of International Science
    Inventors: Tadahiro Ohmi, Shigetoshi Sugawa, Akinobu Teramoto, Hiroshi Akahori, Keiichi Nii
  • Patent number: 8153487
    Abstract: A semiconductor device includes a semiconductor substrate, a first insulating film provided on the semiconductor substrate, a charge storage layer provided on the first insulating film, a second insulating film comprising a plurality of insulating films provided on the charge storage layer and comprising a nitride film as an uppermost layer, and a single-layer control gate electrode provided on the second insulating film and comprising metal silicide.
    Type: Grant
    Filed: March 10, 2010
    Date of Patent: April 10, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Wakako Takeuchi, Hiroshi Akahori, Murato Kawai
  • Patent number: 8133782
    Abstract: A memory device includes a semiconductor substrate, memory elements formed above the substrate in rows and columns, bit lines and word lines selectively connected with the memory elements in the respective columns and rows, each memory element including, a first gate insulator formed above the substrate, a charge accumulation layer formed on the first gate insulator, a second gate insulator formed on the charge accumulation layer, and a control electrode formed on the second gate insulator, wherein a ratio r/d is not smaller than 0.5, where r: a radius of curvature of an upper corner portion or surface roughness of the charge accumulation layer and d: an equivalent oxide thickness of the second gate insulator in a cross section along a direction vertical to the bit lines.
    Type: Grant
    Filed: February 16, 2011
    Date of Patent: March 13, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Akahori, Wakako Takeuchi, Atsuhiro Sato
  • Publication number: 20120032253
    Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.
    Type: Application
    Filed: October 20, 2011
    Publication date: February 9, 2012
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Akahori, Wakako Takeuchi
  • Publication number: 20120018780
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided via a gate insulating film above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a protection film covering the side face of the gate electrode. The method can include etching the semiconductor substrate using the gate electrode as a mask to form the isolation groove. The side face of the gate electrode is covered with the protection film. The method can include forming a first insulating film by oxidizing a surface of the isolation groove to fill a bottom portion of the isolation groove. In addition, the method can include forming a second insulating film on the first insulating film to fill an upper portion of the isolation groove including the side face of the gate electrode.
    Type: Application
    Filed: March 30, 2011
    Publication date: January 26, 2012
    Inventors: Kazuaki Iwasawa, Shigeo Kondo, Hiroshi Akahori, Kiyohito Nishihara, Yingkang Zhang, Masaki Kondo, Hidenobu Nagashima, Takashi Ichikawa
  • Publication number: 20120018783
    Abstract: According to one embodiment, a method is disclosed for manufacturing a semiconductor device. A side face parallel to a channel direction of a plurality of gate electrodes provided above a semiconductor substrate is included as a part of an inner wall of an isolation groove provided between the adjacent gate electrodes. The method can include forming a first isolation groove penetrating through a conductive film serving as the gate electrode to reach the semiconductor substrate. The method can include forming a protection film covering a side wall of the first isolation groove including a side face of the gate electrode. The method can include forming a second isolation groove by etching the semiconductor substrate exposed to a bottom surface of the first isolation groove. The method can include oxidizing an inner surface of the second isolation groove provided on each of both sides of the gate electrode to form first insulating films, which are connected to each other under the gate electrode.
    Type: Application
    Filed: May 27, 2011
    Publication date: January 26, 2012
    Inventors: Kazuaki Iwasawa, Shigeo Kondo, Hiroshi Akahori, Kiyohito Nishihara, Yingkang Zhang, Masaki Kondo, Hidenobu Nagashima, Takashi Ichikawa
  • Publication number: 20120007163
    Abstract: According to one embodiment, a nonvolatile memory device includes a substrate, first and second tunnel insulating films, first and second floating gate electrodes, an intergate insulating film and a control gate electrode. The substrate has first and second active regions isolated from each other by an element isolation trench. The first and second tunnel insulating films are located in the first and second active regions, respectively. The first and second floating gate electrodes are located on the first and second tunnel insulating films, respectively. The intergate insulating film includes a first insulating layer of a first insulating material, an electron trap layer of a second insulating material on the first insulating layer, and a second insulating layer of the first insulating material on the electron trap layer. The control gate electrode is located on the intergate insulating film.
    Type: Application
    Filed: March 21, 2011
    Publication date: January 12, 2012
    Inventors: Hiroshi Akahori, Kiyohito Nishihara, Masaki Kondo, Yingkang Zhang, Shigeo Kondo, Hidenobu Nagashima, Kazuaki Iwasawa, Takashi Ichikawa
  • Patent number: 8071444
    Abstract: A nonvolatile semiconductor memory has a semiconductor substrate, a first insulating film formed on a channel region on a surface portion of the semiconductor substrate, a charge accumulating layer formed on the first insulating film, a second insulating film formed on the charge accumulating layer, a control gate electrode formed on the second insulating film, and a third insulating film including an Si—N bond that is formed on a bottom surface and side surfaces of the charge accumulating layer.
    Type: Grant
    Filed: September 30, 2010
    Date of Patent: December 6, 2011
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Akahori, Wakako Takeuchi
  • Patent number: 8030182
    Abstract: By hydrogen-terminating a semiconductor surface using a solution containing HF2? ions and an oxidant, the hydrogen termination can be quickly carried out. In this case, the semiconductor surface is silicon having a (111) surface, a (110) surface, or a (551) surface.
    Type: Grant
    Filed: September 20, 2005
    Date of Patent: October 4, 2011
    Assignee: Tadahiro OHMI
    Inventors: Tadahiro Ohmi, Akinobu Teramoto, Hiroshi Akahori