Patents by Inventor Hiroshi Ando

Hiroshi Ando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7855447
    Abstract: In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved. The conductive leads of a resin package for supplying a power supply section of a semiconductor integrated circuit chip with power from an external power supply are connected with bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires. Furthermore, the conductive leads connected to a GND for supplying the power supply section of the semiconductor integrated circuit chip with a grounding potential are connected with the bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires.
    Type: Grant
    Filed: March 22, 2007
    Date of Patent: December 21, 2010
    Assignee: Panasonic Corporation
    Inventors: Eisaku Maeda, Hiroshi Ando, Jinsaku Kaneda, Akihiro Maejima, Hiroki Matsunaga
  • Patent number: 7854023
    Abstract: A helmet that can be removed from the head of a helmet wearer who wears the helmet, with a comparatively small force, and simply and quickly including preliminary operation for removal. A recess-projection fitting mechanism to attach a blockish inside pad to a head protecting cap portion includes a male hook on a blockish inside pad side, and a female hook on a head protecting cap portion side. The interrupt portion of a pad takeout member including a pulling means can interrupt between the male hook and female hook to disengage their recess-projection fitting, and can catch on the male hook, and the male hook can be pulled out to outside the head protecting cap portion at least halfway.
    Type: Grant
    Filed: May 3, 2007
    Date of Patent: December 21, 2010
    Assignee: Shoei Co., Ltd.
    Inventor: Hiroshi Ando
  • Patent number: 7851601
    Abstract: Medicaments for treating diseases related to HB-EGF escalation are in demand. The present invention provides a monoclonal antibody or an antibody fragment thereof which binds to a cell membrane-bound HB-EGF, a membrane type HB-EGF and a secretory HB-EGF.
    Type: Grant
    Filed: December 8, 2008
    Date of Patent: December 14, 2010
    Assignee: Kyowa Hakko Kirin Co., Ltd.
    Inventors: Eisuke Mekada, Ryo Iwamoto, Shingo Miyamoto, Kenya Shitara, Akiko Furuya, Kazuyasu Nakamura, Kumiko Takahashi, Hiroshi Ando, Kazuhiro Masuda, Yuka Sasaki
  • Publication number: 20100196392
    Abstract: An object of the present invention is to provide a monoclonal antibody which is useful for treating or diagnosing a disease relating to system ASC amino acid transporter 2 (hereinafter, referred to as “ASCT2”) or a method using the antibody. The present invention provides a monoclonal antibody which specifically recognizes a native three-dimensional structure of an extracellular region of ASCT2 and binds to the extracellular region, or an antibody fragment thereof; a hybridoma which produces the antibody; a DNA which encodes the antibody; a vector which contains the DNA; a transformant obtainable by introducing the vector; a process for producing an antibody or an antibody fragment thereof using the hybridoma or the transformant; and a therapeutic agent using the antibody or the antibody fragment thereof, and a diagnostic agent using the antibody or the antibody fragment thereof.
    Type: Application
    Filed: July 17, 2009
    Publication date: August 5, 2010
    Applicant: Kyowa Hakko Kirin Co., Ltd.
    Inventors: Norihiko SHIRAISHI, Akiko Furuya, Hiroe Toki, Hiroshi Ando, Masayo Suzuki, Tsuguo Kubota
  • Publication number: 20100184958
    Abstract: Medicaments for treating diseases related to HB-EGF escalation are in demand. The present invention provides a monoclonal antibody or an antibody fragment thereof which binds to a cell membrane-bound HB-EGF, a membrane type HB-EGF and a secretory HB-EGF.
    Type: Application
    Filed: December 8, 2008
    Publication date: July 22, 2010
    Applicant: KYOWA HAKKO KIRIN CO., LTD.
    Inventors: EISUKE MEKADA, RYO IWAMOTO, SHINGO MIYAMOTO, KENYA SHITARA, AKIKO FURUYA, KAZUYASU NAKAMURA, KUMIKO TAKAHASHI, HIROSHI ANDO, KAZUHIRO MASUDA, YUKA SASAKI
  • Patent number: 7749056
    Abstract: To provide a game system in which each of the players in turn controls a common character (operation object) so as to enjoy a continuous electric game; and to provide a game system in which a previous player who has been replaced by another player still has willing to participate in the game. There is provided a game system to which a plurality of players can access via respective operation terminals.
    Type: Grant
    Filed: September 27, 2004
    Date of Patent: July 6, 2010
    Assignee: Kabushiki Kaisha Sega
    Inventors: Hiroshi Ando, Shiro Takehara, Akihito Fujiwara
  • Publication number: 20100159835
    Abstract: A wireless blood glucose meter (2) has a blood glucose level detector (21), a transmitter (22), a receiver (23), a storage component (24), and a transmission power determiner (25). Whether or not an acknowledge signal has been received and the transmission power when the transmitter (22) has transmitted a blood glucose level are stored as history information in the storage component (24), and the transmission power determiner (25) determines the transmission power when the transmitter (22) transmits on the basis of the history information stored in the storage component (24).
    Type: Application
    Filed: December 12, 2008
    Publication date: June 24, 2010
    Inventors: Tooru Aoki, Eiji Okuda, Akiyoshi Oozawa, Hiroshi Ando, Kazuo Manabe, Norio Imai
  • Publication number: 20100156861
    Abstract: A display driver includes a shift register; an OR circuit configured to perform an OR operation on data signals respectively representing bits in the shift register which are not adjacent to each other, and to output a result of the OR operation; a delay circuit configured to delay the output of the OR circuit, and to output the delayed output; timing generators respectively corresponding to the data signals, where each of the timing generators generates and outputs a first control signal including a first pulse and a second control signal including a second pulse in accordance with a corresponding one of the data signals and the output of the delay circuit; and output circuits respectively corresponding to the timing generators, where each of the output circuits outputs voltages of a first and a second power supply. A duration of the second pulse includes a duration of the first pulse.
    Type: Application
    Filed: December 3, 2009
    Publication date: June 24, 2010
    Inventors: Tomohisa Sakaguchi, Daijiro Arisawa, Hiroshi Ando, Tetsu Nagano
  • Publication number: 20090302347
    Abstract: A semiconductor integrated circuit includes a plurality of circuit cells each including a pad on a semiconductor chip. Each of the circuit cells includes a high-side transistor, a level shift circuit, a low-side transistor, a pre-driver, and a pad. The high-side transistor and the low-side transistor are arranged to face each other with the pad interposed therebetween.
    Type: Application
    Filed: September 29, 2006
    Publication date: December 10, 2009
    Inventors: Hiroki Matsunaga, Masahiko Sasada, Akihiro Maejima, Jinsaku Kaneda, Hiroshi Ando
  • Publication number: 20090273099
    Abstract: On a semiconductor chip in a semiconductor integrated circuit, a plurality of circuit cells each of which has a pad are formed along a first chip side of the semiconductor chip. Among the plurality of circuit cells, one or more circuit cells at least in the vicinity of an end portion on the first chip side are arranged having a steplike shift in a direction apart from the first chip side with decreasing distance from the center portion to the end portion on the first chip side.
    Type: Application
    Filed: September 29, 2006
    Publication date: November 5, 2009
    Inventors: Hiroki Matsunaga, Akihiro Maejima, Jinsaku Kaneda, Hiroshi Ando, Eisaku Maeda
  • Patent number: 7605220
    Abstract: An object of the present invention is to provide a curing composition which is practically curable and highly adhesive even though a non-organotin compound is included as a curing catalyst. Problems involved are solved by a curing composition characterized by including (A) an organic polymer having one or more silicon-containing groups capable of cross linking by forming siloxane bonds, (B) a metal carboxylate and/or carboxylic acid, and (C) a silicon compound having a hetero atom on the carbon atom in the ? or ? position with respect to the silicon atom.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: October 20, 2009
    Assignee: Kaneka Corporation
    Inventors: Katsuyu Wakabayashi, Toshihiko Okamoto, Hiroshi Ando
  • Publication number: 20090202556
    Abstract: An object of the present invention is to provide a monoclonal antibody which is useful as a diagnostic agent or a therapeutic agent for a disease relating to a polypeptide encoded by Claudin-4 (hereinafter referred to as “CLDN4”) gene or a polypeptide encoded by a Claudin-3 (hereinafter referred to as “CLDN3”) gene, or a method for using the same.
    Type: Application
    Filed: March 17, 2008
    Publication date: August 13, 2009
    Applicant: KYOWA HAKKO KIRIN CO., LTD.
    Inventors: So OHTA, Hiroshi ANDO, Masayo SUZUKI, Shinobu KAWAMOTO, Mariko NAKANO, Kazuyasu Nakamura
  • Publication number: 20090195482
    Abstract: A PDP-driving semiconductor integrated circuit includes a plurality of PDP drivers each for converting an input signal into a high-voltage pulse having an amplitude greater than that of the input signal and outputting the high-voltage pulse. The PDP-driving semiconductor integrated circuit has a function of performing sequential operation in which the PDP drivers operate at different timings and sequentially output the high-voltage pulses and a function of performing simultaneous operation in which the PDP drivers operate at the same timing and output the high-voltage pulses at a time. In each of the sequential operation and the simultaneous operation, at least one of the speed of change in voltage level of the high-voltage pulse from a low level to a high level and the speed of change in voltage level of the high-voltage pulse from the high level to the low level is controlled.
    Type: Application
    Filed: September 29, 2008
    Publication date: August 6, 2009
    Inventors: Eisaku MAEDA, Hiroshi ANDO, Naoki HISHIKAWA, Jinsaku KANEDA, Hiroki MATSUNAGA
  • Patent number: 7561966
    Abstract: A vehicle information display system includes a head-up display for reflecting an image on a windshield of a vehicle and displaying the image so that a driver recognizes the image as a virtual image. Information is collected for being displayed by the head-up display. A circumstance of the vehicle, a circumstance of surrounding of the vehicle, or a circumstance of the driver is detected. The collected information is classified in accordance with a detection result. Then, display contents of the head-up display are controlled in accordance with a classification result.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: July 14, 2009
    Assignee: DENSO CORPORATION
    Inventors: Koji Nakamura, Hiroshi Ando, Akira Kamiya, Nobuaki Kawahara, Kazuya Yasuda, Masaru Kakizaki, Nozomi Kitagawa, Tomoo Aoki, Yoshio Shinoda, Naoyuki Aoki, Shinji Kashiwada, Junya Inada, Akira Takahashi, Takayuki Fujikawa
  • Publication number: 20090167371
    Abstract: It is aimed to reduce the area of an output circuit in a capacitive load driving circuit capable of high voltage output, such as a PDP scan driver for driving a plasma display panel. To achieve this, there are provided an arbitrary number of N-type MOS transistors 001, 002, . . . , and 003 including grounded sources and gates receiving a control signal, diodes 004, 005, . . . , and 006 paired with the N-type MOS transistors 001, 002, . . . , and 003, respectively, and including cathodes connected to drains of the N-type MOS transistors 001, 002, . . . , and 003 and anode, all connected to a first node 044, the number of diodes being the same as the number of N-type MOS transistors, and a first P-type MOS transistor 015 having a drain connected to the first node 044, a gate receiving a control signal and a source connected to a high voltage source.
    Type: Application
    Filed: January 11, 2006
    Publication date: July 2, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroshi Ando, Akihiro Maejima, Hiroki Matsunaga, Jinsaku Kaneda, Eisaku Maeda
  • Patent number: 7550547
    Abstract: The present invention provides a curable composition which has a high recovery ratio, a high creep resistance, a practical curability and storage stability. The present invention relates to a curable composition comprising a reactive silicon group containing organic polymer (A) and a carboxylic acid (B), wherein the composition comprises (I), as the carboxylic acid (B), a carboxylic acid (C) in which the carbon adjacent to the carbonyl group is a quaternary carbon atoms and/or the composition comprises (II) a metal carboxylate (D) formed between a carboxylic acid in which the carbon atoms adjacent to the carbonyl group is a quaternary carbon atoms and a metal atom of 208 or less in atomic weight.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: June 23, 2009
    Assignee: Kaneka Corporation
    Inventors: Katsuyu Wakabayashi, Toshihiko Okamoto, Hiroshi Ando
  • Patent number: 7534820
    Abstract: The present invention provides a novel photocurable composition containing an organic polymer having an epoxy group and/or oxetane group-containing silicon group at an end and a cationic photoinitiator. For example, the photocurable composition contains an organic polymer (A) having an epoxy group and/or oxetane group-containing silicon group at an end, and a cationic photoinitiator (B), the organic polymer (A) being produced by addition reaction between an organic polymer terminated with an unsaturated group and a hydrosilane compound having an epoxy group and/or an oxetane group.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: May 19, 2009
    Assignee: Kaneka Corporation
    Inventors: Yoshiyuki Kohno, Hiroshi Ando
  • Publication number: 20090108434
    Abstract: In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved. The conductive leads of a resin package for supplying a power supply section of a semiconductor integrated circuit chip with power from an external power supply are connected with bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires. Furthermore, the conductive leads connected to a GND for supplying the power supply section of the semiconductor integrated circuit chip with a grounding potential are connected with the bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires.
    Type: Application
    Filed: March 22, 2007
    Publication date: April 30, 2009
    Inventors: Eisaku Maeda, Hiroshi Ando, Jinsaku Kaneda, Akihiro Maejima, Hiroki Matsunaga
  • Publication number: 20090085899
    Abstract: A scan driving circuit includes: a shift register section receiving a scan data signal and a scan clock signal; a plurality of pulse width control circuits each receiving an output signal from the shift register section and a negative pulse width control signal to output a signal whose pulse width is controlled based on the negative pulse width control signal; a blanking section receiving the output signals from the plurality of pulse width control circuits and a blanking signal; and a plurality of high voltage output sections for amplifying the output signals from the plurality of pulse width control circuits, which are received via the blanking section, to successively output negative pulses each having a controlled pulse width to the scanning electrodes.
    Type: Application
    Filed: July 29, 2008
    Publication date: April 2, 2009
    Inventors: Hiroshi ANDO, Seiya Yoshida, Hiroki Matsunaga, Jinsaku Kaneda
  • Publication number: 20090045480
    Abstract: A semiconductor integrated circuit includes a plurality of circuit cells on a semiconductor chip. The plurality of circuit cells are formed along a first chip side of the semiconductor chip. Each of the plurality of circuit cells has a pad. The semiconductor integrated circuit further includes a high voltage potential interconnect formed over the plurality of circuit cells. The high voltage potential interconnect has a width expanding in a length direction from a center portion to end portions of the high voltage potential interconnect.
    Type: Application
    Filed: November 7, 2006
    Publication date: February 19, 2009
    Inventors: Hiroki Matsunaga, Naoki Hishikawa, Akihiro Maejima, Jinsaku Kaneda, Hiroshi Ando