Patents by Inventor Hiroshi Ando

Hiroshi Ando has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7605220
    Abstract: An object of the present invention is to provide a curing composition which is practically curable and highly adhesive even though a non-organotin compound is included as a curing catalyst. Problems involved are solved by a curing composition characterized by including (A) an organic polymer having one or more silicon-containing groups capable of cross linking by forming siloxane bonds, (B) a metal carboxylate and/or carboxylic acid, and (C) a silicon compound having a hetero atom on the carbon atom in the ? or ? position with respect to the silicon atom.
    Type: Grant
    Filed: April 23, 2004
    Date of Patent: October 20, 2009
    Assignee: Kaneka Corporation
    Inventors: Katsuyu Wakabayashi, Toshihiko Okamoto, Hiroshi Ando
  • Publication number: 20090202556
    Abstract: An object of the present invention is to provide a monoclonal antibody which is useful as a diagnostic agent or a therapeutic agent for a disease relating to a polypeptide encoded by Claudin-4 (hereinafter referred to as “CLDN4”) gene or a polypeptide encoded by a Claudin-3 (hereinafter referred to as “CLDN3”) gene, or a method for using the same.
    Type: Application
    Filed: March 17, 2008
    Publication date: August 13, 2009
    Applicant: KYOWA HAKKO KIRIN CO., LTD.
    Inventors: So OHTA, Hiroshi ANDO, Masayo SUZUKI, Shinobu KAWAMOTO, Mariko NAKANO, Kazuyasu Nakamura
  • Publication number: 20090195482
    Abstract: A PDP-driving semiconductor integrated circuit includes a plurality of PDP drivers each for converting an input signal into a high-voltage pulse having an amplitude greater than that of the input signal and outputting the high-voltage pulse. The PDP-driving semiconductor integrated circuit has a function of performing sequential operation in which the PDP drivers operate at different timings and sequentially output the high-voltage pulses and a function of performing simultaneous operation in which the PDP drivers operate at the same timing and output the high-voltage pulses at a time. In each of the sequential operation and the simultaneous operation, at least one of the speed of change in voltage level of the high-voltage pulse from a low level to a high level and the speed of change in voltage level of the high-voltage pulse from the high level to the low level is controlled.
    Type: Application
    Filed: September 29, 2008
    Publication date: August 6, 2009
    Inventors: Eisaku MAEDA, Hiroshi ANDO, Naoki HISHIKAWA, Jinsaku KANEDA, Hiroki MATSUNAGA
  • Patent number: 7561966
    Abstract: A vehicle information display system includes a head-up display for reflecting an image on a windshield of a vehicle and displaying the image so that a driver recognizes the image as a virtual image. Information is collected for being displayed by the head-up display. A circumstance of the vehicle, a circumstance of surrounding of the vehicle, or a circumstance of the driver is detected. The collected information is classified in accordance with a detection result. Then, display contents of the head-up display are controlled in accordance with a classification result.
    Type: Grant
    Filed: December 2, 2004
    Date of Patent: July 14, 2009
    Assignee: DENSO CORPORATION
    Inventors: Koji Nakamura, Hiroshi Ando, Akira Kamiya, Nobuaki Kawahara, Kazuya Yasuda, Masaru Kakizaki, Nozomi Kitagawa, Tomoo Aoki, Yoshio Shinoda, Naoyuki Aoki, Shinji Kashiwada, Junya Inada, Akira Takahashi, Takayuki Fujikawa
  • Publication number: 20090167371
    Abstract: It is aimed to reduce the area of an output circuit in a capacitive load driving circuit capable of high voltage output, such as a PDP scan driver for driving a plasma display panel. To achieve this, there are provided an arbitrary number of N-type MOS transistors 001, 002, . . . , and 003 including grounded sources and gates receiving a control signal, diodes 004, 005, . . . , and 006 paired with the N-type MOS transistors 001, 002, . . . , and 003, respectively, and including cathodes connected to drains of the N-type MOS transistors 001, 002, . . . , and 003 and anode, all connected to a first node 044, the number of diodes being the same as the number of N-type MOS transistors, and a first P-type MOS transistor 015 having a drain connected to the first node 044, a gate receiving a control signal and a source connected to a high voltage source.
    Type: Application
    Filed: January 11, 2006
    Publication date: July 2, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Hiroshi Ando, Akihiro Maejima, Hiroki Matsunaga, Jinsaku Kaneda, Eisaku Maeda
  • Patent number: 7550547
    Abstract: The present invention provides a curable composition which has a high recovery ratio, a high creep resistance, a practical curability and storage stability. The present invention relates to a curable composition comprising a reactive silicon group containing organic polymer (A) and a carboxylic acid (B), wherein the composition comprises (I), as the carboxylic acid (B), a carboxylic acid (C) in which the carbon adjacent to the carbonyl group is a quaternary carbon atoms and/or the composition comprises (II) a metal carboxylate (D) formed between a carboxylic acid in which the carbon atoms adjacent to the carbonyl group is a quaternary carbon atoms and a metal atom of 208 or less in atomic weight.
    Type: Grant
    Filed: March 29, 2005
    Date of Patent: June 23, 2009
    Assignee: Kaneka Corporation
    Inventors: Katsuyu Wakabayashi, Toshihiko Okamoto, Hiroshi Ando
  • Patent number: 7534820
    Abstract: The present invention provides a novel photocurable composition containing an organic polymer having an epoxy group and/or oxetane group-containing silicon group at an end and a cationic photoinitiator. For example, the photocurable composition contains an organic polymer (A) having an epoxy group and/or oxetane group-containing silicon group at an end, and a cationic photoinitiator (B), the organic polymer (A) being produced by addition reaction between an organic polymer terminated with an unsaturated group and a hydrosilane compound having an epoxy group and/or an oxetane group.
    Type: Grant
    Filed: March 13, 2006
    Date of Patent: May 19, 2009
    Assignee: Kaneka Corporation
    Inventors: Yoshiyuki Kohno, Hiroshi Ando
  • Publication number: 20090108434
    Abstract: In a semiconductor integrated circuit device of the present invention, temperature increase of a bonding wire can be suppressed even when conductive leads are short-circuited with each other, and reliability of the semiconductor integrated circuit device is improved. The conductive leads of a resin package for supplying a power supply section of a semiconductor integrated circuit chip with power from an external power supply are connected with bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires. Furthermore, the conductive leads connected to a GND for supplying the power supply section of the semiconductor integrated circuit chip with a grounding potential are connected with the bonding pads of the semiconductor integrated circuit chip by a plurality of bonding wires.
    Type: Application
    Filed: March 22, 2007
    Publication date: April 30, 2009
    Inventors: Eisaku Maeda, Hiroshi Ando, Jinsaku Kaneda, Akihiro Maejima, Hiroki Matsunaga
  • Publication number: 20090085899
    Abstract: A scan driving circuit includes: a shift register section receiving a scan data signal and a scan clock signal; a plurality of pulse width control circuits each receiving an output signal from the shift register section and a negative pulse width control signal to output a signal whose pulse width is controlled based on the negative pulse width control signal; a blanking section receiving the output signals from the plurality of pulse width control circuits and a blanking signal; and a plurality of high voltage output sections for amplifying the output signals from the plurality of pulse width control circuits, which are received via the blanking section, to successively output negative pulses each having a controlled pulse width to the scanning electrodes.
    Type: Application
    Filed: July 29, 2008
    Publication date: April 2, 2009
    Inventors: Hiroshi ANDO, Seiya Yoshida, Hiroki Matsunaga, Jinsaku Kaneda
  • Publication number: 20090045480
    Abstract: A semiconductor integrated circuit includes a plurality of circuit cells on a semiconductor chip. The plurality of circuit cells are formed along a first chip side of the semiconductor chip. Each of the plurality of circuit cells has a pad. The semiconductor integrated circuit further includes a high voltage potential interconnect formed over the plurality of circuit cells. The high voltage potential interconnect has a width expanding in a length direction from a center portion to end portions of the high voltage potential interconnect.
    Type: Application
    Filed: November 7, 2006
    Publication date: February 19, 2009
    Inventors: Hiroki Matsunaga, Naoki Hishikawa, Akihiro Maejima, Jinsaku Kaneda, Hiroshi Ando
  • Patent number: 7469016
    Abstract: A circuit for generating a ternary signal that receives a binary input-control signal and a binary reset signal and outputs a ternary signal. The circuit includes first to third transistors, each source terminal thereof is respectively connected to the three power supplies, and a sequential circuit that outputs control signals controlling the transistors. The sequential circuit outputs control signals that make the first and the third transistors be switched in a complementary manner in an initial state, and make the second and the third transistors be switched in a state that it is released from the initial state.
    Type: Grant
    Filed: November 30, 2005
    Date of Patent: December 23, 2008
    Assignee: Panasonic Corporation
    Inventors: Jinsaku Kaneda, Akihiro Maejima, Hiroki Matsunaga, Eisaku Maeda, Hiroshi Ando
  • Publication number: 20080238814
    Abstract: A head-up display apparatus allows an occupant of a vehicle to visually perceive a virtual image of an image light reflected by a windshield after passing through a cylindrical lens. The cylindrical lens is inclined against the image light to thereby reflect outside light not to reach an eye range of the occupant. The cylindrical lens is placed in a light guide portion such that (i) an action axis direction for an optical action and (ii) a horizontal direction in the display image agree with each other. Of the cylindrical lens, an inclination angle and installation depth are so set that light incident at an angle equal to or greater than an interception upper-limit incident angle and reflected by a pass-through side of the cylindrical lens does not arrive at the eye range of the occupant.
    Type: Application
    Filed: March 27, 2008
    Publication date: October 2, 2008
    Applicant: DENSO CORPORATION
    Inventors: Toshiki ISHIKAWA, Hiroshi ANDO, Takayuki FUJIKAWA
  • Patent number: 7358968
    Abstract: The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
    Type: Grant
    Filed: November 17, 2004
    Date of Patent: April 15, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masahiko Sasada, Hiroki Matsunaga, Masashi Inao, Hiroshi Ando, Jinsaku Kaneda, Eisaku Maeda, Akihiro Maejima
  • Patent number: 7351782
    Abstract: The present invention provides a one-part curable composition, comprising (A) an organic polymer having a silicon-containing group capable of cross-linking by forming siloxane bonds; (B) a metal carboxylate; and (C) a carboxylic acid smaller in molar quantity than the (B) component metal carboxylate, the one-part curable composition being simultaneously practical in recovery ratio, durability, creep resistance, storage stability and adhesion.
    Type: Grant
    Filed: September 22, 2003
    Date of Patent: April 1, 2008
    Assignee: Kaneka Corporation
    Inventors: Katsuyu Wakabayashi, Toshihiko Okamoto, Hiroshi Ando
  • Patent number: 7349672
    Abstract: A digital signal transceiver includes a frequency modulator for outputting a high-frequency signal frequency-modulated with a digital signal input thereto, a power amplifier, an antenna terminal, and an antenna switch. The antenna switch includes a first branch port for receiving a signal output from the power amplifier, a common port connected to the antenna terminal, said common port being connected to the first branch port in the transmitting mode, and a second branch port connected to the common port in the receiving mode. The transceiver further includes a filter having an input port thereof connected to the second branch port of the antenna switch, a high-frequency amplifier having an input port thereof connected to an output port of the filter, and a mixer for mixing a signal output from the high-frequency amplifier with the signal output from the frequency modulator.
    Type: Grant
    Filed: February 19, 2004
    Date of Patent: March 25, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Masaaki Noda, Osamu Asayama, Hiroshi Ando, Hideaki Ueda, Mitsuru Kaito
  • Publication number: 20080068368
    Abstract: The collector, emitter, and base of a bipolar transistor circuit are connected to a high side power supply terminal, the drain of a level shift transistor, and a floating power supply terminal, respectively. When a high side output transistor is on, the floating power supply terminal is at the potential of a high potential power supply terminal. The high side power supply terminal is at a potential higher than the potential of the floating power supply terminal by a constant voltage. Turning the level shift transistor on, its drain potential drops below the potential of the floating power supply terminal; The base current flows through the bipolar transistor circuit and the drain potential of the level shift transistor is clamped near the potential of the floating power supply terminal; The bipolar transistor circuit is turned on and its collector current supplies the drain current of the level shift transistor.
    Type: Application
    Filed: November 16, 2007
    Publication date: March 20, 2008
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Masahiko Sasada, Hiroki Matsunaga, Masashi Inao, Hiroshi Ando, Jinsaku Kaneda, Eisaku Maeda, Akihiro Maejima
  • Patent number: 7323923
    Abstract: A driver circuit is provided for preventing generation of a pass-through current in a CMOS output unit even if a power supply voltage VDD supplied from a low voltage power supply drops below a recommended operating power supply voltage. The driver circuit includes a level shift unit having PMOS transistors and NMOS transistors, and a CMOS output unit having a PMOS transistor and an NMOS transistor. The source, drain and gate of one PMOS transistor are respectively connected to a high voltage power supply, a first contact and a second contact. The source, drain and gate of a second PMOS transistor are respectively connected to a high voltage power supply, the second contact and the first contact. The source of one NMOS transistor is grounded, the drain thereof is connected to the first contact, and the gate thereof receives a low voltage signal. The source of a second NMOS transistor is grounded, the drain thereof is connected to the second contact, and the gate thereof receives a low voltage signal.
    Type: Grant
    Filed: August 26, 2005
    Date of Patent: January 29, 2008
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Eisaku Maeda, Hiroshi Ando, Jinsaku Kaneda, Akihiro Maejima, Hiroki Matsunaga
  • Publication number: 20070288722
    Abstract: The information processing device includes a plurality of integrated circuits that are interconnected via an external bus. Each of the integrated circuits is structured to be connectable via an internal bus to a CPU, a user logic, and a bridge. One integrated circuit is set as a master integrated circuit, which controls other integrated circuits, and the other integrated circuits are set as slave integrated circuits. CPUs of the slave integrated circuits are set in a reset state. Only the CPU of the master integrated circuit can be boot and it controls the user logic of the slave integrated circuit via the bridge of the slave integrated circuit and the external bus.
    Type: Application
    Filed: March 29, 2007
    Publication date: December 13, 2007
    Inventors: Masanori Ando, Yoshitaka Ota, Hiroshi Ando
  • Publication number: 20070273412
    Abstract: A drive voltage supply circuit has a first wire line, a second wire line, a first drive circuit, a plurality of second drive circuits, a control circuit for driving the first drive circuit and the plurality of second drive circuits, and an impedance element connected between the first wire line and each of output terminals.
    Type: Application
    Filed: May 24, 2007
    Publication date: November 29, 2007
    Inventors: Seiya Yoshida, Hiroki Matsunaga, Akihiro Maejima, Jinsaku Kaneda, Hiroshi Ando
  • Publication number: 20070271688
    Abstract: A helmet that can be removed from the head of a helmet wearer who wears the helmet, with a comparatively small force, and simply and quickly including preliminary operation for removal. A recess-projection fitting mechanism to attach a blockish inside pad to a head protecting cap portion includes a male hook on a blockish inside pad side, and a female hook on a head protecting cap portion side. The interrupt portion of a pad takeout member including a pulling means can interrupt between the male hook and female hook to disengage their recess-projection fitting, and can catch on the male hook, and the male hook can be pulled out to outside the head protecting cap portion at least halfway.
    Type: Application
    Filed: May 3, 2007
    Publication date: November 29, 2007
    Inventor: Hiroshi Ando