Abstract: A solid-state imaging device includes: a plurality of pixel cells arranged in a matrix. In the solid-state imaging device, each of the plurality of pixel cells includes: a photoelectric converter that generates charge by photoelectric conversion, and holds a potential according to an amount of the charge generated; an initializer that initializes the potential of the photoelectric converter; a comparison section that compares the potential of the photoelectric converter and a predetermined reference signal, and causes the initializer to perform initialization when the potential of the photoelectric converter and the predetermined reference signal match; and a counter that counts a total number of times of initialization performed by the initializer, and outputs a signal corresponding to the total number of times as a first signal indicating an intensity of incident light.

Abstract: A solid-state imaging device includes: a plurality of pixel cells arranged in a matrix. In the solid-state imaging device, each of the plurality of pixel cells includes: a photoelectric converter that generates charge by photoelectric conversion, and holds a potential according to an amount of the charge generated; an initializer that initializes the potential of the photoelectric converter; a comparison section that compares the potential of the photoelectric converter and a predetermined reference signal, and causes the initializer to perform initialization when the potential of the photoelectric converter and the predetermined reference signal match; and a counter that counts a total number of times of initialization performed by the initializer, and outputs a signal corresponding to the total number of times as a first signal indicating an intensity of incident light.

Abstract: A solid-state imaging device includes a first A/D converter circuit and a second A/D converter circuit per column. The first A/D converter circuit performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal through a binary search, and (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of the digital signal. The second A/D converter circuit performs a second A/D conversion that generates a second digital signal being a low-order portion that is a remainder of the digital signal by measuring a time required for an output of the second comparator to be inverted, the second comparator comparing a quantitative relationship between the analog signal refined and a ramp signal.

Abstract: A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.

Abstract: A solid-state imaging device includes an A/D converter per column. The A/D converter performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal to a range of a potential corresponding to a difference between a first potential and a second potential through a binary search, and further (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of a digital signal. The A/D converter also performs a second A/D conversion that generates, based on a ramp signal and the result of the binary search, a second digital signal being a low-order portion of a remainder of the digital signal, by measuring a time necessary for an output of a second comparator to be inverted.

Abstract: A solid-state imaging device includes a first A/D converter circuit and a second A/D converter circuit per column. The first A/D converter circuit performs a first A/D conversion that (i) refines, using a first comparator, a range including a potential of an analog signal through a binary search, and (ii) generates, based on a result of the binary search, a first digital signal being a high-order portion of the digital signal. The second A/D converter circuit performs a second A/D conversion that generates a second digital signal being a low-order portion that is a remainder of the digital signal by measuring a time required for an output of the second comparator to be inverted, the second comparator comparing a quantitative relationship between the analog signal refined and a ramp signal.

Abstract: A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.

Abstract: A ramp generator circuit includes: a reference signal generator circuit which generates a ramp waveform having a slope obtained by multiplication using a power of 2 according to a value of a higher order bit of a gain control signal; a clock control circuit which selectively outputs 2^m kinds of fractional-N clocks according to one of 2^m (natural number) areas obtained by dividing a code range represented by a lower order bit, when a negative gain is set; and a variable gain circuit which sets a ramp waveform according to the value of the gain control signal, and sets a ramp signal amplitude in each area so that a period ratio between ramp driving clocks for adjacent areas and a ratio between an amplitude of a ramp signal when the standard gain is set and a largest amplitude of a ramp signal are equal.

Abstract: A solid-state imaging device includes the following. Pixels arranged in matrix converts received light into signal voltage. A column AD conversion unit, which includes a comparison unit and an up-down counting unit, converts signal voltage to digital signal. The comparison unit compares a value of signal voltage to a gradually changing value of reference signal voltage. The up-down counting unit counts, by one of down-counting and up-counting, a time period until the comparison result is reversed if the signal voltage is of a base signal component of each pixel at reset level, and counts, by an other of down-counting and up-counting, the time period if the signal voltage is of a superimposed signal component in which the base signal component is superimposed on a pixel signal component corresponding to an amount of light received by the pixel. The comparison unit has switchable kinds of frequency band characteristics.

Abstract: A solid-state imaging device includes: a plurality of unit cells each including at least one light receiving unit and an amplifying transistor which outputs an amplified signal corresponding to an amount of the signal charge photoelectrically converted by the light receiving unit; a plurality of vertical signal lines each for receiving an output signal from the amplifying transistor; a pixel power supply line for supplying a power supply voltage to the amplifying transistor; a plurality of constant current source transistors each connected to a different one of the vertical signal lines; and a bias circuit which controls an amount of current to be supplied to each of the constant current source transistors, based on a variation in the power supply voltage.

Abstract: A voltage generation circuit includes a control circuit which outputs a first digital signal, a DAC which outputs a first analog signal corresponding to the first digital signal, and an attenuator which is connected to an output terminal of the DAC and is configured to output a voltage signal obtained by attenuating the first analog signal input from the DAC.

Abstract: The ramp-signal generator circuit includes a reference voltage generator that changes the voltage of a reference signal Vr to a comparator setting voltage VR for compensating for a voltage difference between a reference signal Vr and an analog input signal (Vs1-Vsn) before comparison by an analog-to-digital converter circuit and outputs a ramp signal whose slope starts from the comparator setting voltage VR in response to a start of the comparison. The ramp-signal generator circuit is configured to add a predetermined enhanced voltage VA to the comparator setting voltage VR before the comparison.

Abstract: A ramp generator circuit includes: a reference signal generator circuit which generates a ramp waveform having a slope obtained by multiplication using a power of 2 according to a value of a higher order bit of a gain control signal; a clock control circuit which selectively outputs 2?m kinds of fractional-N clocks according to one of 2?m (natural number) areas obtained by dividing a code range represented by a lower order bit, when a negative gain is set; and a variable gain circuit which sets a ramp waveform according to the value of the gain control signal, and sets a ramp signal amplitude in each area so that a period ratio between ramp driving clocks for adjacent areas and a ratio between an amplitude of a ramp signal when the standard gain is set and a largest amplitude of a ramp signal are equal.

Abstract: A solid-state imaging device includes the following. Pixels arranged in matrix converts received light into signal voltage. A column AD conversion unit, which includes a comparison unit and an up-down counting unit, converts signal voltage to digital signal. The comparison unit compares a value of signal voltage to a gradually changing value of reference signal voltage. The up-down counting unit counts, by one of down-counting and up-counting, a time period until the comparison result is reversed if the signal voltage is of a base signal component of each pixel at reset level, and counts, by an other of down-counting and up-counting, the time period if the signal voltage is of a superimposed signal component in which the base signal component is superimposed on a pixel signal component corresponding to an amount of light received by the pixel. The comparison unit has switchable kinds of frequency band characteristics.

Abstract: A voltage generation circuit includes a control circuit which outputs a first digital signal, a DAC which outputs a first analog signal corresponding to the first digital signal, and an attenuator which is connected to an output terminal of the DAC and is configured to output a voltage signal obtained by attenuating the first analog signal input from the DAC.

Abstract: The ramp-signal generator circuit includes a reference voltage generator that changes the voltage of a reference signal Vr to a comparator setting voltage VR for compensating for a voltage difference between a reference signal Vr and an analog input signal (Vs1-Vsn) before comparison by an analog-to-digital converter circuit and outputs a ramp signal whose slope starts from the comparator setting voltage VR in response to a start of the comparison. The ramp-signal generator circuit is configured to add a predetermined enhanced voltage VA to the comparator setting voltage VR before the comparison.

Abstract: The solid-state imaging device according to the present invention includes a valid pixel area, a horizontal OB area, and a peripheral circuit area. The valid pixel area includes valid pixel cells from each of which an image signal corresponding to incident light is outputted. The horizontal OB area includes light-blocking pixel cells from each of which a black level signal not depending on the incident light. The peripheral circuit area includes a peripheral circuit. When (i) the valid pixel area has N line layers, (ii) each of the horizontal OB area and the peripheral circuit area has M line layers, and (iii) N<M, an (N+2)th line layer blocks light incident on the horizontal OB area, and an interlayer insulating film is filled between the (N+2)th line layer and the N-th line layer in the horizontal OB area.

Abstract: A digital PID controller controlling a control subject to be in a target state includes: a detector detecting analog data of a current state of the control subject; an AD converter converting the analog data to a digital value; and a digital PID control unit (i) receiving an error value and (ii) digitally performing at least one of integral calculation and derivative calculation to generate a manipulated variable. The digital PID control unit includes at least one of: a first suppression unit suppressing the error value when an absolute value of the error value is equal to or smaller than a first set value; and a second suppression unit suppressing the error value when the absolute value is equal to or smaller than a second set value, and performs the integral calculation and the derivative calculation on the outputs of the first suppression unit and the second suppression unit, respectively.

Abstract: A stepping motor driving apparatus includes a detector that detects a current supplied to a winding included in the stepping motor, a first offset adding section that adds an offset to the output of the detector, an amplifier that amplifies the output of the first offset adding section, a reference signal generator that generates a reference signal indicating a current limit, a second offset adding section that adds an offset to the output of the reference signal generator, a switching section that supplies a power to the winding when the switching section is turned on and cuts off a power to the winding when the switching section is turned off, and a PWM controller that turns on the switching section every predetermined period, and turns off the switching section when the output of the amplifier exceeds the output of the second offset adding section.

Abstract: A stepping motor driving apparatus includes a detector that detects a current supplied to a winding included in the stepping motor, a first offset adding section that adds an offset to the output of the detector, an amplifier that amplifies the output of the first offset adding section, a reference signal generator that generates a reference signal indicating a current limit, a second offset adding section that adds an offset to the output of the reference signal generator, a switching section that supplies a power to the winding when the switching section is turned on and cuts off a power to the winding when the switching section is turned off, and a PWM controller that turns on the switching section every predetermined period, and turns off the switching section when the output of the amplifier exceeds the output of the second offset adding section.