Abstract: A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line.

Abstract: A multichip package according to an embodiment of the invention comprises a first chip and a second chip. A first ground line formed in the first chip and the second ground line formed in the second chip are connected via ESD protection circuits. One of the protection circuits is formed in the first chip and the other is formed in the second chip, allowing effective ESD discharge according to CDM model.

Abstract: A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line.

Abstract: In one embodiment of the present invention, in a discrete MOSFET, the ZTC point is determined by combining the variation of the drain current induced by the variation of the threshold voltage in response to the temperature and the variation of the drain current induced by the variation of the mobility in response to the temperature. The chips configured with a number of circuits, however, include the circuits whose main operation regions of the MOSFETs are different. In CMOS circuits, the MOSFETs operate in the saturation region. On the other hand, in analog circuits, such as sense amplifiers or bandgap circuits, the MOSFETs operate in the linear region. In the design of the temperature dependence of the chip, the design is achieved by independently different models for respective MOSFETs whose operation regions are different.

Abstract: Soft-error resistance and latch up resistance are simultaneously improved for LSI involving miniaturization and reducing operating voltage. Pwells andN wells are formedin a higher density substrate (P on P+ substrate), and buried N wells are formed on a layer underlying thereof. A PMOSFET is formed in the N well and a NMOSFET is formed in the P well. A P well electric potential junction for coupling P well electric potential of the P well to predetermined electric potential is provided, and a region directly under the P well electric potential junction is provided with a region where the aforementioned buried N well is not disposed. The soft-error resistance is improved by having the buried N well therein, and the latch up resistance is improved by coupling the P well to the substrate.

Abstract: A semiconductor memory device includes (a) a plurality of reference cells, (b) a plurality of memory cells, data stored in a selected reference cell among the reference cells being compared to data stored in a selected memory cell among the memory cells, (c) an address transition detector for detecting transition in input of addresses by which a memory cell is selected among the memory cells, and transmitting an address transition detecting signal indicative of the detected transition, (d) a counter for counting the address transition detecting signals, and (e) a reference cell decoder for selecting a reference cell among the reference cells in accordance with an output transmitted from the counter.

Abstract: A protection element comprises a ring-shape gate electrode, an N+ drain region inside the ring-shape gate electrode, an N+ source region outside, and a shield plate electrode. The ring gate and source regions are connected to ground via a through-hole, and the drain region is connected to an external pad. The shield plate electrode is connected to ground or to a power supply. Element isolation is achieved by the shield plate electrode, without forming a LOCOS or other element isolation oxide layer. By this means, blocking of thermal conduction by an oxide layer can be avoided to improve the heat dissipation and ESD resistance of the protection element.

Abstract: In a memory system, an ECC circuit is not inserted on a data path for data writing/reading. The ECC process is performed during the cycle of normal data reading/writing process, in such timing that it does not conflict with the data reading/writing process in order not to cause a substantial delay in the data writing/reading process. Specifically, the ECC process is performed during the cycle of burst transfer in which a plurality of data are successively input to or output from a shift register. Since no access is made to the memory cell array during the burst transfer cycle, the ECC process does not cause a delay in the reading/writing process.

Abstract: A semiconductor integrated circuit device is disclosed that can provide greater flexibility of layout while essentially ensuring circuit characteristics, and at the same time providing an minimum electrostatic discharge breakdown withstand value according to Charged Device Model (CDM) at all input/output (I/O) terminals. For each I/O terminal a size of a CDM protective device can be optimized in response to reference electric potential wiring resistance between an input protective device, a MOSFETs that can constitute an internal circuit, and an input resistance.

Abstract: A semiconductor memory device includes (a) a plurality of reference cells, (b) a plurality of memory cells, data stored in a selected reference cell among the reference cells being compared to data stored in a selected memory cell among the memory cells, (c) an address transition detector for detecting transition in input of addresses by which a memory cell is selected among the memory cells, and transmitting an address transition detecting signal indicative of the detected transition, (d) a counter for counting the address transition detecting signals, and (e) a reference cell decoder for selecting a reference cell among the reference cells in accordance with an output transmitted from the counter.

Abstract: A hybrid gas insulation switchgear apparatus comprises an enclosure in which an insulating gas is sealed, a bushing unit provided for the enclosure, a breaker unit disposed inside the enclosure, a disconnector unit disposed inside the enclosure and including disconnectors to be connected electrically in series to both sides of the breaker unit, an earth switch unit disposed inside the enclosure and including earth switches disposed between the breaker unit and the disconnectors, respectively, the earth switches being provided with main pole side electrodes disposed on the side of the breaker unit, and a current transformer unit mounted to the enclosure. The bushing unit including bushings each having a conductor connected to an electrode in the disconnector on a side opposite to the breaker.

Abstract: The present invention provides a switchgear, which can achieve miniaturization and simplification while securing high operation reliability, and excellent in assembly, operability and inspection, and further, has a compact size. A fluid pressure operating section is provided in a mechanical box arranged on a lower end portion of a support porcelain tube. Insulated operating rods are received in the support porcelain tube, and connecting mechanisms are received in a container. Switching contacts of circuit breaker and disconnecting switches and the fluid pressure operating section are connected via the connecting mechanisms and the insulated operating rods.

Abstract: A semiconductor memory device, adapted for storing plural bits per cell to be able to accomplish high storage density by a simplified structure, includes a plurality of first gate electrodes extending parallel to one another along one direction and a plurality of second gate electrodes extending in a direction of intersecting the first gate electrodes, in which a diffusion region is provided on each of a plurality of divisions demarcated in a matrix-like pattern by first and second electrodes on a substrate surface. One of the divisions, the four sides of which are defined by two neighboring first gate electrodes and two neighboring second gate electrodes, has four independently accessible bits, and is connected by a contact (CT) with a diffusion region in the division. There are provided a plurality of interconnections connected via contacts to the diffusion regions of other divisions in the plural matrix-like divisions lying on the line of extension of the aforementioned diagonal line.

Abstract: A hybrid gas insulation switchgear apparatus comprises an enclosure in which an insulating gas is sealed, a bushing unit provided for the enclosure, a breaker unit disposed inside the enclosure, a disconnector unit disposed inside the enclosure and including disconnectors to be connected electrically in series to both sides of the breaker unit, an earth switch unit disposed inside the enclosure and including earth switches disposed between the breaker unit and the disconnectors, respectively, the earth switches being provided with main pole side electrodes disposed on the side of the breaker unit, and a current transformer unit mounted to the enclosure. The bushing unit including bushings each having a conductor connected to an electrode in the disconnector on a side opposite to the breaker.

Abstract: In a hybrid type gas insulation switch gear apparatus, a main enclosure including a first cylindrical section have a base and a second cylindrical section branched from the base. A bushing is mounted on the cylindrical section and including a hollow insulating housing having a housing space and a central conductor extended in the hollow insulating housing. A first insulating spacer is provided in the first cylindrical section and configured to separate the first hollow space into first and second segment spaces. An insulating enclosure is also mounted to the second cylindrical section and including an enclosure space. A second insulating spacer is provided between the insulating enclosure and the second cylindrical section and configured to separate the enclosure space from the second hollow space. A disconnecting switch is formed in the first segment space of the first cylindrical section and a circuit breaker is also formed in the insulating enclosure.

Abstract: A hybrid gas insulation switchgear apparatus comprises an enclosure in which an insulating gas is sealed, a bushing unit provided for the enclosure, a breaker unit disposed inside the enclosure, a disconnector unit disposed inside the enclosure and including disconnectors to be connected electrically in series to both sides of the breaker unit, an earth switch unit disposed inside the enclosure and including earth switches disposed between the breaker unit and the disconnectors, respectively, the earth switches being provided with main pole side electrodes disposed on the side of the breaker unit, and a current transformer unit mounted to the enclosure. The bushing unit including bushings each having a conductor connected to an electrode in the disconnector on a side opposite to the breaker.

Abstract: The present invention provides a switchgear, which can achieve miniaturization and simplification while securing high operation reliability, and excellent in assembly, operability and inspection, and further, has a compact size. A fluid pressure operating section is provided in a mechanical box arranged on a lower end portion of a support porcelain tube. Insulated operating rods are received in the support porcelain tube, and connecting mechanisms are received in a container. Switching contacts of circuit breaker and disconnecting switches and the fluid pressure operating section are connected via the connecting mechanisms and the insulated operating rods.

Abstract: In a hybrid type gas insulation switch gear apparatus, a main enclosure including a first cylindrical section have a base and a second cylindrical section branched from the base. A bushing is mounted on the cylindrical section and including a hollow insulating housing having a housing space and a central conductor extended in the hollow insulating housing. A first insulating spacer is provided in the first cylindrical section and configured to separate the first hollow space into first and second segment spaces. An insulating enclosure is also mounted to the second cylindrical section and including an enclosure space. A second insulating spacer is provided between the insulating enclosure and the second cylindrical section and configured to separate the enclosure space from the second hollow space. A disconnecting switch is formed in the first segment space of the first cylindrical section and a circuit breaker is also formed in the insulating enclosure.

Abstract: A semiconductor integrated circuit device is disclosed that can provide greater flexibility of layout while essentially ensuring circuit characteristics, and at the same time providing an minimum electrostatic discharge breakdown withstand value according to Charged Device Model (CDM) at all input/output (I/O) terminals. For each I/O terminal a size of a CDM protective device can be optimized in response to reference electric potential wiring resistance between an input protective device, a MOSFETs that can constitute an internal circuit, and an input resistance.

Abstract: A hybrid gas insulation switchgear apparatus comprises an enclosure in which an insulating gas is sealed, a bushing unit provided for the enclosure, a breaker unit disposed inside the enclosure, a disconnector unit disposed inside the enclosure and including disconnectors to be connected electrically in series to both sides of the breaker unit, an earth switch unit disposed inside the enclosure and including earth switches disposed between the breaker unit and the disconnectors, respectively, the earth switches being provided with main pole side electrodes disposed on the side of the breaker unit, and a current transformer unit mounted to the enclosure. The bushing unit including bushings each having a conductor connected to an electrode in the disconnector on a side opposite to the breaker.