Abstract: The mounting apparatus includes: a bonding head 14 that bonds, while pressing, a semiconductor chip 100 onto a substrate 110 or another semiconductor chip 100; and a heating mechanism 16 that heats the semiconductor chip 100 from the side during the execution of this bonding. After two or more semiconductor chips 100 are stacked while being bonded by temporary pressure-bonding, the bonding head 14 heats and applies pressure to an upper surface of the resultant stacked body, thereby integrally pressure-bonding the two or more semiconductor chips 100, and at the time of this pressure-bonding the heating mechanism 16 heats the stacked body from the side.

Abstract: The mounting apparatus includes: a bonding head 14 that bonds, while pressing, a semiconductor chip 100 onto a substrate 110 or another semiconductor chip 100; and a heating mechanism 16 that heats the semiconductor chip 100 from the side during the execution of this bonding. After two or more semiconductor chips 100 are stacked while being bonded by temporary pressure-bonding, the bonding head 14 heats and applies pressure to an upper surface of the resultant stacked body, thereby integrally pressure-bonding the two or more semiconductor chips 100, and at the time of this pressure-bonding the heating mechanism 16 heats the stacked body from the side.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: Technique capable of achieving reliability improvement of a semiconductor device even if temperature rising of an operation guarantee temperature of the semiconductor device is performed is provided. Gap portions are provided among a plurality of pads, and a glass coat composed of, for example, a silicon oxide film or a silicon nitride film is embedded in the gap portions. The glass coat is provided in order to secure electrical insulation among the pads, and coats outer edge portions of the pads. Trenches are formed so as to be adjacent to regions, which are coated with the glass coat, of the outer edge portions of the pads.

Abstract: Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (? portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region.

Abstract: There is provided a technology capable of suppressing the damage applied to a pad. When the divergence angle of an inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is very small in magnitude. In other words, the ultrasonic conversion load in a direction perpendicular to the surface of the pad is sufficiently smaller in magnitude than the ultrasonic conversion load in a direction in parallel with the surface of the pad. Consequently, when the divergence angle of the inner chamfer part is smaller than 90 degrees, the ultrasonic conversion load in a direction perpendicular to the surface of the pad can be sufficiently reduced in magnitude, which can prevent pad peeling.

Abstract: Height control of a capillary is performed in a stitch bonding (2nd bond) in a wire bonding, so that a thickness of a stitch portion can be controlled, thereby ensuring a bonding strength at the stitch portion and achieving an improvement in a bonding reliability. Also, the stitch portion has a thick portion, and a wire and a part (? portion) of a bonding region of an inner lead is formed to a lower portion of the thick portion, thereby sufficiently ensuring a thickness of the stitch portion and a bonding region.

Abstract: A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said multiple kinds of interlayer insulating films; the interlayer insulating film of a low elastic modulus having the lowest elastic modulus and having an opening located under the metal pad, the interlayer insulating film of a not-low elastic modulus having the elastic modulus larger than the elastic modulus of the interlayer insulating film of the low elastic modulus, being layered in contact with the interlayer insulating film of the low elastic modulus, and continuously extending over the opening and a region surrounding the opening and a metal interconnection layer arranged under the metal pad, filling the opening in the interlayer insulating film of the low elastic modulus, and being in contact with the interlayer insulating film of the not-low elastic modulus.

Abstract: A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said multiple kinds of interlayer insulating films; the interlayer insulating film of a low elastic modulus having the lowest elastic modulus and having an opening located under the metal pad, the interlayer insulating film of a not-low elastic modulus having the elastic modulus larger than the elastic modulus of the interlayer insulating film of the low elastic modulus, being layered in contact with the interlayer insulating film of the low elastic modulus, and continuously extending over the opening and a region surrounding the opening and a metal interconnection layer arranged under the metal pad, filling the opening in the interlayer insulating film of the low elastic modulus, and being in contact with the interlayer insulating film of the not-low elastic modulus.

Abstract: In order to provide a downsized semiconductor device increased in function level with output terminals arranged along at least three sides of a semiconductor chip, the semiconductor device includes a semiconductor chip having a row of aggregated pads arranged on a main surface, and a row of output terminals arranged along at least three sides at a perimeter of the semiconductor chip, wire-bonded with the row of aggregated pads.

Abstract: In order to provide a downsized semiconductor device increased in function level with output terminals arranged along at least three sides of a semiconductor chip, the semiconductor device includes a semiconductor chip having a row of aggregated pads arranged on a main surface, and a row of output terminals arranged along at least three sides at a perimeter of the semiconductor chip, wire-bonded with the row of aggregated pads.

Abstract: A semiconductor device includes: multiple kinds of interlayer insulating films formed on a semiconductor substrate and having different elastic moduli, respectively; a metal pad arranged on said multiple kinds of interlayer insulating films; the interlayer insulating film of a low elastic modulus having the lowest elastic modulus and having an opening located under the metal pad, the interlayer insulating film of a not-low elastic modulus having the elastic modulus larger than the elastic modulus of the interlayer insulating film of the low elastic modulus, being layered in contact with the interlayer insulating film of the low elastic modulus, and continuously extending over the opening and a region surrounding the opening and a metal interconnection layer arranged under the metal pad, filling the opening in the interlayer insulating film of the low elastic modulus, and being in contact with the interlayer insulating film of the not-low elastic modulus.

Abstract: A semiconductor device comprises a chip; a plurality of bonding pads provided on the chip; and a plurality of inner leads arranged opposite to the bonding pads. Further the semiconductor device comprises a plurality of bonding wires electrically connecting the bonding pads and the corresponding inner leads, respectively. Each of the bonding wires has a plurality of bends electrically isolated from conductive parts on the chip, and the bonding pads are arranged at optional positions on a surface of the chip. Hence the shorting of the chip by the bonding wires can be reliably prevented, the bonding wire having a high mechanical strength can be stably fed, the bonding pads may be optionally arranged on the chip, the degree of freedom of designing the layout of the internal circuit of the chip is high, and the semiconductor device and the wire bonding apparatus can be developed at a high efficiency.

Abstract: At least one of a corner portion of the semiconductor chip, a corner portion of the sealing member, and a portion in which two neighboring gold wires are spaced at a larger distance than any other two neighboring gold wires adjacent to the two neighboring gold wires is configured such that one electrode and another electrode adjacent to it are arranged in such a way that the space between one gold wire connected to one electrode and another gold wire connected to another electrode and adjacent to one gold wire is substantially equal to the diameter of these gold wires when one gold wire has been displaced toward another gold wire due to a flow of a resin at a time of sealing with the resin.