Patents by Inventor Hiroshi Horibe

Hiroshi Horibe has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6787927
    Abstract: A semiconductor device comprises a chip; a plurality of bonding pads provided on the chip; and a plurality of inner leads arranged opposite to the bonding pads. Further the semiconductor device comprises a plurality of bonding wires electrically connecting the bonding pads and the corresponding inner leads, respectively. Each of the bonding wires has a plurality of bends electrically isolated from conductive parts on the chip, and the bonding pads are arranged at optional positions on a surface of the chip. Hence the shorting of the chip by the bonding wires can be reliably prevented, the bonding wire having a high mechanical strength can be stably fed, the bonding pads may be optionally arranged on the chip, the degree of freedom of designing the layout of the internal circuit of the chip is high, and the semiconductor device and the wire bonding apparatus can be developed at a high efficiency.
    Type: Grant
    Filed: January 18, 2002
    Date of Patent: September 7, 2004
    Assignee: Renesas Technology Corp.
    Inventor: Hiroshi Horibe
  • Patent number: 6600218
    Abstract: A semiconductor device comprises a semiconductor chip. The semiconductor chip has an internal active region, an external active region, and a plurality of electrodes for electrically connecting the internal active region and the external active region to outside thereof, respectively. The semiconductor device also comprises a boarding portion that carries the semiconductor chip, a plurality of external electrode terminals for electrical connection to an external device, a plurality of connecting wires each connecting the electrode of the semiconductor chip and the external electrode terminal; and a mold resin that seals the semiconductor chip, the boarding portion and the connecting wires. The electrodes are disposed around the internal active region, and the external active region is disposed outside the electrodes.
    Type: Grant
    Filed: May 24, 2002
    Date of Patent: July 29, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fumiaki Aga, Namiki Moriga, Hiroshi Horibe, Yasuhito Suzuki, Akira Takaki
  • Publication number: 20030052394
    Abstract: A semiconductor device comprises a semiconductor chip. The semiconductor chip has an internal active region, an external active region, and a plurality of electrodes for electrically connecting the internal active region and the external active region to outside thereof, respectively. The semiconductor device also comprises a boarding portion that carries the semiconductor chip, a plurality of external electrode terminals for electrical connection to an external device, a plurality of connecting wires each connecting the electrode of the semiconductor chip and the external electrode terminal; and a mold resin that seals the semiconductor chip, the boarding portion and the connecting wires. The electrodes are disposed around the internal active region, and the external active region is disposed outside the electrodes.
    Type: Application
    Filed: May 24, 2002
    Publication date: March 20, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Fumiaki Aga, Namiki Moriga, Hiroshi Horibe, Yasuhito Suzuki, Akira Takaki
  • Publication number: 20030042622
    Abstract: A semiconductor device comprises a chip; a plurality of bonding pads provided on the chip; and a plurality of inner leads arranged opposite to the bonding pads. Further the semiconductor device comprises a plurality of bonding wires electrically connecting the bonding pads and the corresponding inner leads, respectively. Each of the bonding wires has a plurality of bends electrically isolated from conductive parts on the chip, and the bonding pads are arranged at optional positions on a surface of the chip. Hence the shorting of the chip by the bonding wires can be reliably prevented, the bonding wire having a high mechanical strength can be stably fed, the bonding pads may be optionally arranged on the chip, the degree of freedom of designing the layout of the internal circuit of the chip is high, and the semiconductor device and the wire bonding apparatus can be developed at a high efficiency.
    Type: Application
    Filed: January 18, 2002
    Publication date: March 6, 2003
    Applicant: Mitsubishi Denki Kabushiki Kaisha
    Inventor: Hiroshi Horibe
  • Patent number: 6518652
    Abstract: A semiconductor package includes a semiconductor chip, a die pad, an adhesive, metal wires, LOC inner leads, and standard inner leads sealed within a sealing resin. The LOC inner leads and the standard inner leads are arranged in the same plane and both are arranged along one side of the semiconductor chip. Clearance between the inner leads and the die pad larger than the total thickness of the semiconductor chip and the bonding material. Thus, a semiconductor chip having electrode pads broadly distributed can be employed and the section modulus of the semiconductor package can be increased.
    Type: Grant
    Filed: March 15, 2001
    Date of Patent: February 11, 2003
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Yasuki Takata, Hiroshi Horibe, Kazunari Michii
  • Publication number: 20020027279
    Abstract: The present invention provides a semiconductor package in which a semiconductor chip, a die pad, an adhesive, metal wires, LOC type inner and standard type inner leads are sealed with a sealing resin. The LOC type inner leads and the standard type inner leads are arranged on a same plane and mixedly arranged along a side of the semiconductor chip. Clearance between the inner leads and the die pad is set to be larger than a sum of thickness of the semiconductor chip and the bonding material. Thus, a semiconductor chip having electrode pads broadly distributed and arranged thereon can be employed and the modulus of section of the semiconductor package can be enhanced.
    Type: Application
    Filed: March 15, 2001
    Publication date: March 7, 2002
    Inventors: Yasuki Takata, Hiroshi Horibe, Kazunari Michii
  • Patent number: 6112969
    Abstract: A wire bonding method for joining a metal wire with a bonding pad disposed on a semiconductor element by using a load and supersonic wave vibration, comprising: during interval of time from contact of the metal wire with the bonding pad to application of the supersonic wave vibration, continuously applying a first bonding load and a second bonding load which is lower than the first bonding load; and after application of the supersonic wave vibration, continuously applying a third bonding load of a size of about 50% of the load of the second bonding load and a fourth bonding load which is lower than the first bonding load and higher than the third bonding load. The reliability of the fine wire bonding joint is improved remarkably, whereby a high quality semiconductor device cna be produced at a low cost.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: September 5, 2000
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Horibe, Kazuko Nakamura, Shinji Toyosaki
  • Patent number: 6105848
    Abstract: A wire bonding method for joining a metal wire with a bonding pad disposed on a semiconductor element by using a load and supersonic wave vibration, comprising: during interval of time from contact of the metal wire with the bonding pad to application of the supersonic wave vibration, continuously applying a first bonding load and a second bonding load which is lower than the first bonding load; and after application of the supersonic wave vibration, continuously applying a third bonding load of a size of about 50% of the load of the second bonding load and a fourth bonding load which is lower than the first bonding load and higher than the third bonding load. The reliability of the fine wire bonding joint is improved remarkably, whereby a high quality semiconductor device can be produced at a low cost.
    Type: Grant
    Filed: July 30, 1998
    Date of Patent: August 22, 2000
    Assignee: Mitsubishi Denki Kabushki Kaisha
    Inventors: Hiroshi Horibe, Kazuko Nakamura, Shinji Toyosaki
  • Patent number: 5838071
    Abstract: A wire bonding method for joining a metal wire with a bonding pad disposed on a semiconductor element by using a load and supersonic wave vibration, comprising: during interval of time from contact of the metal wire with the bonding pad to application of the supersonic wave vibration, continuously applying a first bonding load and a second bonding load which is lower than the first bonding load; and after application of the supersonic wave vibration, continuously applying a third bonding load of a size of about 50% of the load of the second bonding load and a fourth bonding load which is lower than the first bonding load and higher than the third bonding load. The reliability of the fine wire bonding joint is improved remarkably, whereby a high quality semiconductor device cna be produced at a low cost.
    Type: Grant
    Filed: April 16, 1997
    Date of Patent: November 17, 1998
    Assignee: Mitsubishi Denki Kabushiki Kaisha
    Inventors: Hiroshi Horibe, Kazuko Nakamura, Shinji Toyosaki