Abstract: A display device for complex transmission reflection characteristics processes the amplitude and phase of input complex number data, and displays the processed amplitude and phase. A number of types of coordinate chart image data are stored in a memory and displayed, and chart image data selection circuitry selectively reads one or more types of the coordinate chart image data from the coordinate chart data memory, in response to an input display command signal. A gain controller/phase shifter gain-controls the amplitude and phase of the input complex number data, to correspond to the selected image coordinate data, and signal-processing circuitry superposes the one or more types of selected chart image data and complex number data processed by the gain controller/phase shifter. The input complex number data is then displayed in a desired one or more types of coordinate systems.

Abstract: A frequency converter receives a signal to be measured and a local oscillation signal supplied from a local oscillator and ouputs an intermediate frequency signal. A phase detector detects a phase of the intermediate frequency signal. An A/D converter outputs a digital value corresponding to a phase detection output. A memory stores a plurality of aperture values. Each of the aperture values is read out with a predetermined frequency band which is incremented at a predetermined step. A first controller causes the local oscillator to oscillate signals having first and second frequencies separated from each other by the aperture value in the vicinity of a desired measurement frequency. An arithmetic unit calculates a group delay time of the signal to be measured in accordance with the two digital values and the aperture value corresponding to the respective phase detection outputs when the local oscillator oscillates the signals having the first and second frequencies.

Abstract: Measuring signals whose frequencies stepwise vary with time are fed to a test port of a reflection signal separator through an input port. A through transmission path and short- and open-circuiting elements are selectively connected to the test port. The reflection signal separator has an output port to allow a reflection signal from the test port and transmission signal passed via the through transmission path to be stored in first to third memory circuits through first and second heterodyne receivers equipped with a level correction function. A calculation circuit allows output signals of the first and second heterodyne receivers when an object to be measured is connected to the test port to be calibrated with the use of memory contents of first, second and third memory means so that the output signals are displayed on a display device.

Abstract: A signal analyzing means performs frequency sweep for input signals to be measured, and outputs vector data corresponding to sampling frequencies. The analyzing means supplies pulses to a sweep marker generating means at timings for causing the signal analyzing means to supply the vector data corresponding to the sampling frequencies to the display means. Whenever the sweep marker generating means receives a pulse from the signal analyzing means, it outputs address data for extending a sweep marker. The display means includes a CRT and displays a designated polar coordinate image on the CRT screen. The display means translates the vector data to address data of a position suitable for the polar coordinate image. The address data and sweep marker address data are superposed on polar coordinate data displayed on the CRT screen. The vector data and the sweep marker are simultaneously displayed on the CRT screen.

Abstract: A signal analyzer outputs polar coordinate data to be displayed on an image display unit employing a raster scan scheme. First and second image memories having memory formats corresponding to the screen of the image display unit are provided. A memory switching circuit switches the first and second image memories at each measurement scan so that either one of the first and second memories is set at a write side and a remaining one is set at a deletion side. The polar coordinate data is sequentially written in one of the first and second image memories, data of a previous scan written in the other of the memories is sequentially deleted, and data of both memories are read out simultaneously, so that the polar coordinate data is displayed on the image display unit of the raster scan scheme without discontinuity and in a real time manner.

Abstract: A signal-measuring apparatus for measuring a level of a signal to be measured includes a reference signal oscillator, a variable local signal oscillator, a heterodyne type mixer, a bandpass filter and automatic detuning correction means. In the automatic detuning correction means, there are provided a peak value memory, a tracking circuit and a detuning-correction calculating circuit. When a filter output is obtained by passing the reference signal through the bandpass filter, a peak value is acquired by varying the oscillator frequency of the local signal. This peak value is stored in the peak value memory. Then, the signal to be measured is supplied to the bandpass filter to acquire another filter output. This filter output is calculated in the detuning correction calculating circuit based upon the above-described peak value as a reference value so as to correct the error caused by the filter detuning.

Abstract: A phase detector is disclosed in which means are provided for sensing when two AC signals being subjected to phase difference measurement become close in phase, within a predetermined range, and for inverting one of these signals in phase when such a close phase relationship is sensed. The phase difference between the phase inverted signal and the other signal is then measured, and compensation is applied to the measured results such as to compensate for the effects of the phase inversion operation. Insensitivity and "hunting" effects which occur with prior art phase detectors in the region of zero phase difference are thereby eliminated, and an output signal can be obtained which varies in a smooth and continuous manner with variations in the phase difference between the two signals under measurement, over a 360.degree. range.

Abstract: In a multiprocessory system comprising a plurality of CPUs interconnected by a common bus, means are provided whereby the CPUs are periodically and cyclically enabled to access the bus. Data transfer from one CPU to another is performed by first storing the data into a main memory connected to the bus, then transferring the data from main memory to the destination CPU when the latter is enabled to utilize the bus and is in a condition to accept the data. Means can also be provided whereby, when data must be immediately transferred from one CPU to another, the sending CPU stores the data in main memory, generates signals whereby the destination CPU is given use of the bus, and generates an interrupt which causes transfer of the stored data into the destination CPU.