Patents by Inventor Hiroshi Kagata

Hiroshi Kagata has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120028247
    Abstract: A plasmon sensor includes a first metal layer and a second metal layer having an upper surface facing a lower surface of the first metal layer. The upper surface of the first metal layer is configured to receive an electromagnetic wave. A hollow space is provided between the first and second metal layers, and is configured to be filled with a test sample containing a medium. This plasmon sensor has a small size and a simple structure.
    Type: Application
    Filed: April 20, 2010
    Publication date: February 2, 2012
    Applicant: PANASONIC CORPORATION
    Inventors: Masaya Tamura, Hiroshi Kagata
  • Patent number: 7864025
    Abstract: There is provided a static electricity countermeasure component including a varistor layer having a plurality of inner electrodes of a planer shape, embedded therein a board including alumina laminated with the varistor layer, and a terminal connected to the inner electrode of the varistor layer and formed at a side face of the varistor layer, in which the varistor layer and the board are sintered to thereby diffuse bismuth oxide of the varistor layer in the board and provide a bismuth oxide diffusing layer at the board. In this way, the static electricity countermeasure component achieving thin-sized formation while maintaining a varistor characteristic against a small surge voltage can be realized.
    Type: Grant
    Filed: March 24, 2005
    Date of Patent: January 4, 2011
    Assignee: Panasonic Corporation
    Inventors: Hidenori Katsumura, Tatsuya Inoue, Hiroshi Kagata
  • Patent number: 7826196
    Abstract: The present invention relates to a ceramic laminated device including a dielectric ceramic and an Ag electrode. In a dielectric ceramic that can be sintered at low temperatures and has a high dielectric constant and Q value, reactivity between the ceramic and Ag during sintering is suppressed low and segregation of specific elements in the proximity of the electrode is controlled. Thus, a filter having a high Q value and low loss is produced stably. For this purpose, in a ceramic laminated body including at least a ceramic and a Si-containing glass, a ratio of A/B, i.e. a ratio of a Si element concentration (A) within a range at a distance of 5 ?m or smaller from the Ag electrode to a Si element concentration (B) within a range at a distance larger than 5 ?m from the Ag electrode, is set equal to or smaller than 2.
    Type: Grant
    Filed: March 6, 2007
    Date of Patent: November 2, 2010
    Assignee: Panasonic Corporation
    Inventors: Ryuichi Saito, Koichi Shigeno, Hiroshi Kagata
  • Publication number: 20100089624
    Abstract: Disclosed is a multi-layer ceramic substrate including a glass ceramic and an external terminal formed on a surface of the glass ceramic. The external terminal includes conductive materials mainly composed of at least one among Ag, Au, Pt and Pd, and added with at least one element among Bi, Cu, Ge, Mn, Ti and Zn. Inorganic oxide particles are provided on a surface of the external terminal. The multi-layer ceramic substrate can keep adhesive strength being unchanged after humidity test or after plating and can prevent plating sag and solder leach from occurring.
    Type: Application
    Filed: February 12, 2008
    Publication date: April 15, 2010
    Inventors: Hidekazu Tamai, Nobuyuki Aoki, Satoshi Tomioka, Hiroshi Kagata
  • Patent number: 7592886
    Abstract: A dielectric porcelain composition of the present invention includes a first component and second component. If the first component is represented by the general formula of xBaO-yNd2O3-zTiO2-wBi2O3 (provided that x+y+z+w=100), x, y, z, and w satisfy 12?x?16, 12?y?16, 65?z?69, and 2?w?5, respectively. The second component includes 30 to 37 wt % of BaO, 33 to 46 wt % of SiO2, 8 to 12 wt % of La2O3, 3 to 7 wt % of Al2O3, 0 to 1 wt % of SrO, 0 to 10 wt % of Li2O, 0 to 20 wt % of ZnO, and 7 wt % or less of B203. The compounding ratio of the second component is between 10 wt % and 30 wt % when the sum of the first and second components is 100. In addition, 0.1 to 1 parts by weight of Li2O and 3 to 10 parts by weight of ZnO, relative to 100 parts by weight of the sum of the first and second components, is also contained as a third component. An average particle diameter of the dielectric mixed powder forming dielectric porcelain composition before firing is 0.9 ?m or less.
    Type: Grant
    Filed: March 22, 2006
    Date of Patent: September 22, 2009
    Assignee: Panasonic Corporation
    Inventors: Ryuichi Saito, Hiroshi Kagata, Hidenori Katsumura, Muneyuki Sawada
  • Publication number: 20090230596
    Abstract: An un-sintered multi-layered body includes a first ceramic layer having a surface, a conductor provided on the surface of the first ceramic layer, an insulator provided on the surface of the first ceramic layer and covering an end of the conductor, and a second ceramic layer provided on the conductor and the insulator. The un-sintered multi-layered body is baked at a temperature at which the first ceramic layer can be sintered but the second ceramic layer cannot be sintered. After the un-sintered multi-layered body is baked, the second ceramic layer is removed, thereby providing a multi-layered ceramic substrate. The insulator has a thickness not smaller than 10 ?m and not larger than 40 ?m. This method makes the insulator dense and allows the conductor to be formed easily.
    Type: Application
    Filed: October 31, 2006
    Publication date: September 17, 2009
    Inventors: Muneyuki Sawada, Hidenori Katsumura, Hiroshi Kagata
  • Publication number: 20090201628
    Abstract: In a multilayer ceramic capacitor including: a laminated body layer formed by alternately laminating dielectric layers made of ceramic particles and internal electrodes; and a pair of external electrodes provided on at least both end surfaces of the laminated body layer and alternately connected to the internal electrodes electrically, the number of boundaries between ceramic particles per unit length of the dielectric layer in the lamination direction is larger than that in the direction connecting the pair of external electrodes. Thus increasing the number of ceramic grain boundaries between internal electrodes improves the insulation characteristic. Particularly, even if the number of ceramic particles thicknesswise decreases due to lamellation, increasing the number of grain boundaries suppresses deterioration of the insulation characteristic.
    Type: Application
    Filed: March 14, 2008
    Publication date: August 13, 2009
    Inventors: Hiroshi Kagata, Satoshi Tomioka, Koichi Shigeno
  • Publication number: 20090033441
    Abstract: A dielectric porcelain composition of the present invention includes a first component and second component. If the first component is represented by the general formula of xBaO—yNd2O3-zTiO2-wBi2O3 (provided that x+y+z+w=100), x, y, z, and w satisfy 12?x?16, 12?y?16, 65?z?69, and 2?w?5, respectively. The second component includes 30 to 37 wt % of BaO, 33 to 46 wt % of SiO2, 8 to 12 wt % of La2O3, 3 to 7 wt % of Al2O3, 0 to 1 wt % of SrO, 0 to 10 wt % of Li2O, 0 to 20 wt % of ZnO, and 7 wt % or less of B203. The compounding ratio of the second component is between 10 wt % and 30 wt % when the sum of the first and second components is 100. In addition, 0.1 to 1 parts by weight of Li2O and 3 to 10 parts by weight of ZnO, relative to 100 parts by weight of the sum of the first and second components, is also contained as a third component. An average particle diameter of the dielectric mixed powder forming dielectric porcelain composition before firing is 0.9 ?m or less.
    Type: Application
    Filed: March 22, 2006
    Publication date: February 5, 2009
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Ryuichi Saito, Hiroshi Kagata, Hidenori Katsumura, Muneyuki Sawada
  • Publication number: 20090034157
    Abstract: The present invention relates to a ceramic laminated device including a dielectric ceramic and an Ag electrode. In a dielectric ceramic that can be sintered at low temperatures and has a high dielectric constant and Q value, reactivity between the ceramic and Ag during sintering is suppressed low and segregation of specific elements in the proximity of the electrode is controlled. Thus, a filter having a high Q value and low loss is produced stably. For this purpose, in a ceramic laminated body including at least a ceramic and a Si-containing glass, a ratio of A/B, i.e. a ratio of a Si element concentration (A) within a range at a distance of 5 ?m or smaller from the Ag electrode to a Si element concentration (B) within a range at a distance larger than 5 ?m from the Ag electrode, is set equal to or smaller than 2.
    Type: Application
    Filed: March 6, 2007
    Publication date: February 5, 2009
    Inventors: Ryuichi Saito, Koichi Shigeno, Hiroshi Kagata
  • Publication number: 20070248802
    Abstract: A laminated ceramic component includes a first laminating sheet, a second laminating sheet, a first electrode pattern and a second electrode pattern. The first and the second electrode patterns are located between the first and the second laminating sheets. The second electrode pattern is wider and thinner than the first electrode pattern.
    Type: Application
    Filed: September 30, 2005
    Publication date: October 25, 2007
    Applicant: MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
    Inventors: Ryuichi Saito, Hiroshi Kagata
  • Patent number: 7283032
    Abstract: It is possible to realize an electrostatic discharge protection component having a very small electrostatic capacity suited to a high-frequency equipment and comprising a ceramic insulating substrate, a varistor unit composed of a varistor layer and an internal electrode, which are sintered and integrated on the ceramic insulating substrate, and at least a pair of external electrodes provided on the varistor unit, the varistor unit being formed with a varistor.
    Type: Grant
    Filed: March 10, 2005
    Date of Patent: October 16, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tatsuya Inoue, Hidenori Katsumura, Hiroshi Kagata
  • Patent number: 7277003
    Abstract: An electrostatic discharge protection component of an array type includes ceramic insulating substrate 12; varistor region 10 which is pasted on ceramic insulating substrate 12 and then is sintered integrally with ceramic insulating substrate 12; and at least one ground outer electrode 15A and a plurality of input/output outer electrodes 15B. Varistor region 10 includes at least one ground inner electrode 14A, varistor layer 10C and the plurality of input/output outer electrodes 15B so as to form the plurality of varistors. Ground inner electrode 14A is connected with ground outer electrode 15A. This structure enables the protection component to be extremely thin.
    Type: Grant
    Filed: April 29, 2005
    Date of Patent: October 2, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Tatsuya Inoue, Hidenori Katsumura, Hiroshi Kagata
  • Publication number: 20070171025
    Abstract: There is provided a static electricity countermeasure component including a varistor layer having a plurality of inner electrodes of a planer shape, embedded therein a board including alumina laminated with the varistor layer, and a terminal connected to the inner electrode of the varistor layer and formed at a side face of the varistor layer, in which the varistor layer and the board are sintered to thereby diffuse bismuth oxide of the varistor layer in the board and provide a bismuth oxide diffusing layer at the board. In this way, the static electricity countermeasure component achieving thin-sized formation while maintaining a varistor characteristic against a small surge voltage can be realized.
    Type: Application
    Filed: March 24, 2005
    Publication date: July 26, 2007
    Inventors: Hidenori Katsumura, Tatsuya Inoue, Hiroshi Kagata
  • Patent number: 7231712
    Abstract: A module includes a ceramic substrate, first and second electrodes provided on the ceramic substrate, a component having third and fourth electrodes connected to the first and second electrodes, respectively, and a resin filled in a space between the component and the ceramic substrate. The ceramic substrate has a surface thereof having a recess formed therein. The first and second electrodes are provided on the surface of the ceramic substrate so that the recess is located between the first and second electrodes. The component is located over the recess and spaced from the ceramic substrate with a space including the recess. The space including the recess is filled with the resin. The module allows each component to be surface mounted at higher bonding strength, thus preventing short-circuit between the electrodes on the substrate and improving the operation reliability.
    Type: Grant
    Filed: September 29, 2004
    Date of Patent: June 19, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Ryuichi Saito, Hiroshi Kagata, Masaaki Katsumata
  • Patent number: 7189297
    Abstract: A method of manufacturing an Electro Static Discharge (ESD) protection componentin which slurry including varistor particles and a resin binder is produced, and a varistor green sheet is formed from this slurry. A conductor layer is formed on a surface of the varistor green sheet. A adhesive layer is formed on a baked ceramic substrate, the varistor green sheet is adhered to the adhesive layer and then baked. The method produces a high-performance and uniform ESD protection component.
    Type: Grant
    Filed: December 6, 2004
    Date of Patent: March 13, 2007
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidenori Katsumura, Tatsuya Inoue, Hiroshi Kagata
  • Publication number: 20060227473
    Abstract: It is possible to realize an electrostatic discharge protection component having a very small electrostatic capacity suited to a high-frequency equipment and comprising a ceramic insulating substrate, a varistor unit composed of a varistor layer and an internal electrode, which are sintered and integrated on the ceramic insulating substrate, and at least a pair of external electrodes provided on the varistor unit, the varistor unit being formed with a varistor.
    Type: Application
    Filed: March 10, 2005
    Publication date: October 12, 2006
    Inventors: Tatsuya Inoue, Hidenori Katsumura, Hiroshi Kagata
  • Patent number: 7098160
    Abstract: A dielectric ceramics includes a main ingredient, and a supplemental ingredient in an amount of 0.05 to 2 wt % for the main ingredient. The main ingredient is expressed by xBiO3/2-yCaO-zNbO5/2 and is within a scope of a specified quadrilateral region in a ternary system diagram, and the supplemental ingredient is a glass composition including at least SiO2, Li2O and MO (M includes at least one of Ca, Sr and Ba). A ceramic electronic component is produced by co-firing a dielectric layer composed of the dielectric ceramics and a conductive layer mainly composed of silver, and has a low degradation in Q value and excellent microwave characteristics.
    Type: Grant
    Filed: August 6, 2004
    Date of Patent: August 29, 2006
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hidenori Katsumura, Ryuichi Saito, Hiroshi Kagata
  • Patent number: 6941650
    Abstract: By using a method for manufacturing a dielectric laminated device, an opening is formed on a first dielectric sheet, a strip line and an input and output line including an input and output electrode are formed by burying electrode materials in said opening, the first dielectric sheet is laminated with the second and third dielectric sheets disposed above and below respectively to form a laminate, a first and second shield electrodes and a ground electrode are formed, an end of the strip line is connected to the ground electrode, the first shield electrode and the second shield electrode are mutually connected through the ground electrode, and the input and output electrode is exposed along the line direction of the strip line. By this constitution of the above dielectric laminated device, the mounting reliability of the dielectric laminated device can be further increased.
    Type: Grant
    Filed: September 24, 2002
    Date of Patent: September 13, 2005
    Assignee: Matsushita Electric Industrial Co., Ltd.
    Inventors: Hideaki Nakakubo, Toshio Ishizaki, Toru Yamada, Hiroshi Kagata, Tatsuya Inoue, Shoichi Kitazawa
  • Publication number: 20050195549
    Abstract: An electrostatic discharge protection component of an array type includes ceramic insulating substrate 12; varistor region 10 which is pasted on ceramic insulating substrate 12 and then is sintered integrally with ceramic insulating substrate 12; and at least one ground outer electrode 15A and a plurality of input/output outer electrodes 15B. Varistor region 10 includes at least one ground inner electrode 14A, varistor layer 10C and the plurality of input/output outer electrodes 15B so as to form the plurality of varistors. Ground inner electrode 14A is connected with ground outer electrode 15A. This structure enables the protection component to be extremely thin.
    Type: Application
    Filed: April 29, 2005
    Publication date: September 8, 2005
    Inventors: Tatsuya Inoue, Hidenori Katsumura, Hiroshi Kagata
  • Publication number: 20050141166
    Abstract: The present invention relates to a method of manufacturing an ESD protection component, where the method includes at least a step of producing slurry including varistor particles and a resin binder; a step of producing a varistor green sheet from this slurry; a step of forming a conductor layer; a step of forming an adhesive layer on a ceramic substrate; a step of sticking a varistor green sheet on an adhesive layer; and a step of baking, providing a high-performance and uniform ESD protection component.
    Type: Application
    Filed: December 6, 2004
    Publication date: June 30, 2005
    Inventors: Hidenori Katsumura, Tatsuya Inoue, Hiroshi Kagata