Patents by Inventor Hiroshi Kambayashi

Hiroshi Kambayashi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9875899
    Abstract: The semiconductor transistor according the present invention includes an active layer composed of a GaN-based semiconductor and a gate insulating film formed on the active layer. The gate insulating film has a first insulating film including one or more compounds selected from the group consisting of Al2O3, HfO2, ZrO2, La2O3, and Y2O3 formed on the active layer, and a second insulating film composed of SiO2 formed on the first insulating film.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: January 23, 2018
    Assignees: FUJI ELECTRIC CO., LTD., TOHOKU UNIVERSITY
    Inventors: Hiroshi Kambayashi, Katsunori Ueno, Takehiko Nomura, Yoshihiro Sato, Akinobu Teramoto, Tadahiro Ohmi
  • Patent number: 9230799
    Abstract: A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO2 film and an Al2O3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.
    Type: Grant
    Filed: January 23, 2012
    Date of Patent: January 5, 2016
    Assignees: TOHOKU UNIVERSITY, Fuji Electric Co., Ltd., TOKYO ELECTRON LIMITED
    Inventors: Akinobu Teramoto, Hiroshi Kambayashi, Hirokazu Ueda, Yuichiro Morozumi, Katsushige Harada, Kazuhide Hasebe, Tadahiro Ohmi
  • Patent number: 9048302
    Abstract: A field effect transistor has an MOS structure and is formed of a nitride based compound semiconductor. The field effect transistor includes a substrate; a semiconductor operating layer having a recess and formed on the substrate; an insulating layer formed on the semiconductor operating layer including the recess; a gate electrode formed on the insulating layer at the recess; and a source electrode and a drain electrode formed on the semiconductor operating layer with the recess in between and electrically connected to the semiconductor operating layer. The recess includes a side wall inclined relative to the semiconductor operating layer.
    Type: Grant
    Filed: January 8, 2009
    Date of Patent: June 2, 2015
    Assignee: THE FURUKAWA ELECTRIC CO., LTD
    Inventors: Yoshihiro Sato, Hiroshi Kambayashi, Yuki Niiyama, Takehiko Nomura, Seikoh Yoshida, Masayuki Iwami, Jiang Li
  • Patent number: 8999788
    Abstract: Provided is a method of manufacturing a gallium-nitride-based semiconductor device, comprising forming a first semiconductor layer of a gallium-nitride-based semiconductor; and forming a recessed portion by dry etching a portion of the first semiconductor layer via a microwave plasma process using a bromine-based gas.
    Type: Grant
    Filed: July 24, 2013
    Date of Patent: April 7, 2015
    Assignees: Tohoku University, Furukawa Electric Co., Ltd.
    Inventors: Hiroshi Kambayashi, Akinobu Teramoto, Tadahiro Ohmi
  • Publication number: 20150069410
    Abstract: A semiconductor device includes: a base; an electron transit layer layered on the base; an electron-supplying layer being configured by layering a plurality of AlN layers and GaN layers alternately on the electron transit layer and having an average Al composition x; an etching sacrificial layer layered on the electron-supplying layer and made of AlyGa1-yN (0<y<1) having an Al composition y; a field plate layer layered on the etching sacrificial layer and made of AlzGa1-zN (0?z<1, z<y) having an Al composition z; and an electrode connected to the etching sacrificial layer and being provided in an area in which a part of the field plate layer is removed until reaching the etching sacrificial layer.
    Type: Application
    Filed: November 19, 2014
    Publication date: March 12, 2015
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Kazuyuki UMENO, Hiroshi Kambayashi, Keishi Takaki
  • Publication number: 20140367699
    Abstract: The method for fabricating a semiconductor device is to fabricate a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes a step of forming a gate insulating film. In the step, at least one film selected from the group consisting of a SiO2 film and an Al2O3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.
    Type: Application
    Filed: September 2, 2014
    Publication date: December 18, 2014
    Applicants: TOHOKU UNIVERSITY, FUJI ELECTRIC CO., LTD., TOKYO ELECTRON LIMITED
    Inventors: Akinobu TERAMOTO, Hiroshi KAMBAYASHI, Hirokazu UEDA, Yuichiro MOROZUMI, Katsushige HARADA, Kazuhide HASEBE, Tadahiro OHMI
  • Patent number: 8906796
    Abstract: A method of producing a semiconductor transistor involving formation of an ohmic electrode on an active layer composed of a GaN-based semiconductor includes a process of forming a first layer 11 composed of tantalum nitride on an active layer 3 and a second layer 12 composed of Al layered on the first layer 11 and a process of forming ohmic electrodes 9s and 9d in ohmic contact with the active layer 3 by heat treating the first layer 11 and the second layer 12 at a temperature of from 520° C. to 600° C.
    Type: Grant
    Filed: March 2, 2011
    Date of Patent: December 9, 2014
    Assignee: Tohoku University
    Inventors: Hiroshi Kambayashi, Akinobu Teramoto, Tadahiro Ohmi
  • Publication number: 20130309828
    Abstract: Provided is a semiconductor device manufacturing method, comprising forming a first sacrificial layer that contacts at least a portion of a first semiconductor layer and has a higher solid solubility for impurities included in the first semiconductor layer than the first semiconductor layer; annealing the first sacrificial layer and the first semiconductor layer; removing the first sacrificial layer through a wet process; after removing the first sacrificial layer, performing at least one of forming an insulating layer that covers at least a portion of the first semiconductor layer and etching a portion of the first semiconductor layer; and forming an electrode layer that is electrically connected to the first semiconductor layer.
    Type: Application
    Filed: July 24, 2013
    Publication date: November 21, 2013
    Applicants: Tohoku University, Advanced Power Device Research Association
    Inventors: Hiroshi KAMBAYASHI, Akinobu TERAMOTO, Tadahiro OHMI
  • Publication number: 20130307063
    Abstract: Provided is a method of manufacturing a gallium-nitride-based semiconductor device, comprising forming a first semiconductor layer of a gallium-nitride-based semiconductor; and forming a recessed portion by dry etching a portion of the first semiconductor layer via a microwave plasma process using a bromine-based gas.
    Type: Application
    Filed: July 24, 2013
    Publication date: November 21, 2013
    Applicants: TOHOKU UNIVERSITY, ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Hiroshi KAMBAYASHI, Akinobu TERAMOTO, Tadahiro OHMI
  • Publication number: 20130292700
    Abstract: A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO2 film and an Al2O3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.
    Type: Application
    Filed: January 23, 2012
    Publication date: November 7, 2013
    Applicants: TOHOKU UNIVERSITY, TOKYO ELECTRON LIMTED, Advanced Power Device Research Association
    Inventors: Akinobu Teramoto, Hiroshi Kambayashi, Hirokazu Ueda, Yuichiro Morozumi, Katsushige Harada, Kazuhide Hasebe, Tadahiro Ohmi
  • Patent number: 8525225
    Abstract: A semiconductor device includes a plurality of electrodes arranged on a compound semiconductor layer grown on a substrate, and a surface protection film that protects a surface of a semiconductor layer on the compound semiconductor layer between the electrodes. A refractive index of the surface protection film is controlled so that a stress caused by the surface protection film on the surface of the semiconductor layer is minimized.
    Type: Grant
    Filed: August 29, 2006
    Date of Patent: September 3, 2013
    Assignee: The Furukawa Electric Co., Ltd.
    Inventors: Hiroshi Kambayashi, Nariaki Ikeda, Seikoh Yoshida
  • Publication number: 20130052816
    Abstract: A method of producing a semiconductor transistor involving formation of an ohmic electrode on an active layer composed of a GaN-based semiconductor includes a process of forming a first layer 11 composed of tantalum nitride on an active layer 3 and a second layer 12 composed of Al layered on the first layer 11 and a process of forming ohmic electrodes 9s and 9d in ohmic contact with the active layer 3 by heat treating the first layer 11 and the second layer 12 at a temperature of from 520° C. to 600° C.
    Type: Application
    Filed: March 2, 2011
    Publication date: February 28, 2013
    Applicants: TOHOKU UNIVERISTY, ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Hiroshi Kambayashi, Akinobu Teramoto, Tadahiro Ohmi
  • Publication number: 20130032819
    Abstract: The semiconductor transistor according the present invention includes an active layer composed of a GaN-based semiconductor and a gate insulating film formed on the active layer. The gate insulating film has a first insulating film including one or more compounds selected from the group consisting of Al2O3, HfO2, ZrO2, La2O3, and Y2O3 formed on the active layer, and a second insulating film composed of SiO2 formed on the first insulating film.
    Type: Application
    Filed: March 2, 2011
    Publication date: February 7, 2013
    Applicants: TOHOKU UNIVERISTY, ADVANCED POWER DEVICE RESEARCH ASSOCIATION
    Inventors: Hiroshi Kambayashi, Katsunori Ueno, Takehiko Nomura, Yoshihiro Sato, Akinobu Teramoto, Tadahiro Ohmi
  • Patent number: 8350293
    Abstract: A p-type nitride compound semiconductor layer is formed on a buffer formed on a substrate. An n-type contact region is formed by ion implantation under a source electrode and a drain electrode. An electric-field reducing layer made of an n-type nitride compound semiconductor is formed on the p-type nitride compound semiconductor layer. A carrier density of the electric-field reducing layer is lower than that of the n-type contact region. A first end portion of the electric-field reducing layer contacts with the n-type contact region, and a second end portion of the electric-field reducing layer overlaps with a gate electrode.
    Type: Grant
    Filed: December 29, 2009
    Date of Patent: January 8, 2013
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Tat-Sing Paul Chow, Takehiko Nomura, Yuki Niiyama, Hiroshi Kambayashi, Seikoh Yoshida
  • Patent number: 8304809
    Abstract: In a GaN-based semiconductor device, an active layer of a GaN-based semiconductor is formed on a silicon substrate. A trench is formed in the active layer and extends from a top surface of the active layer to a depth reaching the silicon substrate. A first electrode is formed on an internal wall surface of the trench and extends from the top surface of the active layer to the silicon substrate. A second electrode is formed on the active layer to define a current path between the first electrode and the second electrode via the active layer in an on-state of the device. A bottom electrode is formed on a bottom surface of the silicon substrate and defines a bonding pad for the first electrode. The first electrode is formed of metal in direct ohmic contact with both the silicon substrate and the active layer.
    Type: Grant
    Filed: November 13, 2008
    Date of Patent: November 6, 2012
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Shusuke Kaya, Seikoh Yoshida, Masatoshi Ikeda, legal representative, Sadahiro Kato, Takehiko Nomura, Nariaki Ikeda, Masayuki Iwami, Yoshihiro Sato, Hiroshi Kambayashi, Koh Li
  • Patent number: 8093626
    Abstract: Provided is a normally-off field effect transistor using a III-nitride semiconductor. The transistor is provided with a III-nitride semiconductor layer grown on a substrate by including an acceptor and a donor; a gate insulating film which is formed on the III-nitride semiconductor layer to have a thickness to be at a prescribed threshold voltage based on the concentration of the acceptor and that of the donor; a gate electrode formed on the gate insulating film; a first source/drain electrode formed on the III-nitride semiconductor layer to one side of and separate from the gate electrode, directly or via a high dopant concentration region; and a second source/drain electrode formed away from the gate electrode and the first source/drain electrode, on or under the III-nitride semiconductor layer, directly or via a high dopant concentration region.
    Type: Grant
    Filed: June 14, 2007
    Date of Patent: January 10, 2012
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Yuki Niiyama, Shinya Ootomo, Tatsuyuki Shinagawa, Takehiko Nomura, Seikoh Yoshida, Hiroshi Kambayashi
  • Patent number: 8072002
    Abstract: A field effect transistor formed of a semiconductor of a III group nitride compound, includes an electron running layer formed on a substrate and formed of GaN; an electron supplying layer formed on the electron running layer and formed of AlxGa1-xN (0.01?x?0.4), the electron supplying layer having a band gap energy different from that of the electron running layer and being separated with a recess region having a depth reaching the electron running layer; a source electrode and a drain electrode formed on the electron supplying layer with the recess region in between; a gate insulating film layer formed on the electron supplying layer for covering a surface of the electron running layer in the recess region; and a gate electrode formed on the gate insulating film layer in the recess region. The electron supplying layer has a layer thickness between 5.5 nm and 40 nm.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: December 6, 2011
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Yuki Niyama, Seikoh Yoshida, Hiroshi Kambayashi, Takehiko Nomura, Masayuki Iwami, Shinya Ootomo
  • Patent number: 7998848
    Abstract: The laser beam with a wavelength having a higher energy than the band gap energy of the material forming the carrier moving layer is irradiated to activate the impurities contained in the constituent layer of the field effect transistor in the method of producing the field effect transistor. The method of the invention does not apply the heating of the substrate or the sample stage to raise the temperature of the semiconductor layer using the thermal conductivity so as to activate the impurities. Thus, the implanted impurities can be activated without deteriorating the performance of the device and reliability.
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: August 16, 2011
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Yuki Niiyama, Seikoh Yoshida, Masatoshi Ikeda, legal representative, Hiroshi Kambayashi, Takehiko Nomura
  • Publication number: 20110049529
    Abstract: Provided is a GaN series semiconductor element, which is capable of obtaining an adequate normally-off characteristic, and a manufacturing method thereof. In a GaN series semiconductor element that comprises an operating layer comprising a GaN series compound semiconductor, a gate insulating film that is formed on the operating layer, and a gate electrode that is formed on the gate insulating film, the gate insulating is a SiO2 film of which an infrared absorption peak that corresponds to the vibration energy of a Si—H bond does not appear in the absorption spectrum of transmitted light that is obtained by the Fourier transform infrared spectroscopy method. This kind of SiO2 film is a high-quality SiO2 film in which the occurrence of Si—H bonds and dangling bonds is suppressed. With this kind of construction, adverse effects on the control of the threshold value of the GaN series semiconductor element are also suppressed, so an adequate normally-off characteristic is obtained.
    Type: Application
    Filed: November 10, 2010
    Publication date: March 3, 2011
    Applicant: FURUKAWA ELECTRIC CO., LTD.
    Inventors: Yoshihiro Sato, Takehiko Nomura, Hiroshi Kambayashi, Shinji Nagata
  • Patent number: 7855155
    Abstract: An optical absorption layer comprised of a substance having a band gap energy smaller than that of GaN is formed on an implanted region formed in a pGaN layer as a ground layer. There is performed an annealing step from an upper surface of a substrate with predetermined light such as infrared light, a red light, or the like, which has energy smaller than the band gap energy of the pGaN layer. The optical absorption layer has an absorption coefficient of the light in the annealing step larger than that of the pGaN layer. Accordingly, it is possible to selectively perform a heat treatment on a region directly under the optical absorption layer or a region in a vicinity thereof (the implanted region).
    Type: Grant
    Filed: March 26, 2009
    Date of Patent: December 21, 2010
    Assignee: Furukawa Electric Co., Ltd.
    Inventors: Yuki Niiyama, Hiroshi Kambayashi, Takehiko Nomura, Seikoh Yoshida, Masatoshi Ikeda, legal representative