Abstract: A man-machine interface system for a process controller according to the present invention enables its direct picture select button function to be effectively used by each user, and is improved in the operability of picture selection for interrupt display. The system includes a display, a picture data controller for controlling the pictures, which are displayed on the display, and at least one direct picture select button for requesting the display of an interrupt picture on the display to set control requirements and monitor operating conditions with the controller. In response to the interrupt picture display request by the button, a specified picture is displayed as an interruption on the display. The system further includes an interrupt picture definition table for setting by the user to changeably define on a user's setting picture the picture for interrupt display. The interrupt picture set by the user can be displayed independently of the initialization hierarchy by only operating the button.

Abstract: An apparatus for a feed-back control of an injection molding machine, comprising a control target which operational conditions are different in accordance with operational purposes; and a control unit for subjecting said control target to a feed-back control, is characterized in that said control unit comprises a judgement function section for judging operational purposes of the control target, a condition setting section for setting operational conditions in accordance with the operational purposes and a switching section for switching the condition setting section through the judgement function section.

Abstract: An information processor comprises an instruction decoder for executing a subroutine calling instruction including designation of a general-purpose register for calling a subroutine, a circuit for selecting a specific general-purpose register designated by an instruction based on a result of the execution of a subroutine calling instruction among a plurality of general-purpose registers, and a circuit for saving, in a selected general-purpose register, a value obtained by adding a length of a subroutine calling instruction to a program counter value as a return address.

Abstract: Either a data input key window of step switches type or a data input key window of step numeric keys type is displayed with data item indicating blocks or set value indicating blocks displayed when a touch is made to any one of the data item indicating blocks or the set value indicating blocks according to the selected data input method. If the step switch input method is selected, a value to be set is entered by making touches to increment and decrement keys included in the data input key window. If the numeric key input method is selected, a value is entered by making touches to numeric keys included in the data input key window.

Abstract: In a data processor, an internal memory stores instruction codes and a central processing unit reads an instruction code form the memory and produces an external access request if it contains an instruction to access an external memory which is connected to an external terminal. A bus controller is responsive to the request for producing a data timing signal and one of read and write signals. An external address bus and an external data bus are connected to the bus controller. An internal address bus is connected to the CPU for transporting an internal address signal.

Abstract: An information processing apparatus with a write protection function for a target storage area is provided, which includes a holding section for a write enable flag for indicating whether writing is to be permitted to the target storage area, and a write control section for permitting an intended write operation to the target storage area when the write enable flag held by the holding section indicates the same is to be permitted. The apparatus further includes a setting section for setting the write enable flag in the holding section when a dummy write instruction is executed for a command address, and a resetting section for resetting the write enable flag in the holding section when the intended write operation to the target storage area is executed. The resetting section may further include a section for resetting the write enable flag in the holding section when a predetermined number of instructions or bus cycles are executed after the dummy write instruction.

Abstract: A data processing system includes an instruction decoder for decoding a string of instructions including an arithmetic operation instruction, an arithmetic operation unit controlled by the instruction decoder for executing a designated arithmetic operation for a received data, the arithmetic operation unit outputting not only the result of the designated arithmetic operation, but also a sign information and an overflow/underflow information of the result of the designated arithmetic operation, and a saturation detecting circuit receiving the sign information and the overflow/underflow information for controlling a selector in such a manner that if an overflow has occurred when the sign information indicates the positive, the selector selects a positive maximum value; if an underflow has occurred when the sign information indicates the negative, the selector selects a negative maximum value; and if neither the overflow nor the underflow has occurred, the selector selects the result of arithmetic operation outp

Abstract: A single-chip microcomputer includes a program ROM storing a program; a central processing unit executing the program read out from the program ROM for performing data processing; an external data input port for receiving data to be processed by the central processing unit, from an external device; and an external data output port for outputting data processed by the central processing unit to an external device. The program ROM also stores a test program for testing the program ROM and a plurality of bytes of collation information. The central processing unit has a test mode for executing the test program, and compares the plurality of bytes of collation information with a corresponding number of bytes of data sequentially input through the external input port.

Abstract: A memory control system comprises a plurality of base address registers each for designating a base address of a corresponding memory block, and a corresponding number of block size registers each for designating the size of the corresponding memory block. An output of one base address register and an output of be corresponding block size register are supplied to a corresponding comparator, and compared with MSB bits of a memory access address. An output of the comparator selectively activates, in accordance with the order of priority, a corresponding memory control register which designates a wait state number for the corresponding memory block, so that the wait state number is outputted.

Abstract: An emulation system for emulating an application specific integrated circuit (ASIC) type microcomputer including a central processing unit, a user specific peripheral function unit and a user specific logic circuit, which are integrated together on a single chip. The emulation system includes a first integrated circuit for emulating the central processing unit, and second and third integrated circuits each of which comprises the ASIC-type microcomputer. Each of the second and third integrated circuits can selectively operate in a first evaluation chip mode in which the central processing unit and the user specific logic circuit are isolated from an internal bus, and in a second evaluation chip mode in which the central processing unit and the user specific peripheral function unit are isolated from the internal bus. The first integrated circuit is connected through an peripheral bus to the internal bus of each of the second and third integrated circuits.

Abstract: A microcomputer includes a plurality of peripheral circuits accessed by a central processing unit for a reading/writing of the peripheral circuits. Each of the external terminals supplies a selection signal indicative of use or non-use of a corresponding peripheral circuit. Each selection signal is supplied to a gate circuit provided for the corresponding peripheral circuit, for controlling permission and inhibition of application of a clock signal or a strobe signal to the corresponding peripheral circuit. Thus, neither the clock nor the strobe signal is supplied to the peripheral circuits which are not used in an actual application system, with the result that a low power consumption, highly reliable microcomputer is realized.

Abstract: A microcomputer provided with test mode switching function includes an execution control unit to control the operation of an operation unit, an bus control unit connected via an internal bus to the operation unit and the execution control unit and a test mode control unit to control the switching to the test mode. The execution control unit has a micro address generating unit capable of generating a particular address to execute a microinstruction which separates the operation unit from the internal bus according to a test mode specification signal from the test mode control unit. Alternatively, the execution control unit has an instruction register capable of outputting, to the micro address generating unit, the instruction code of the microinstruction which separates the operation unit from the internal bus.

Abstract: An information processing apparatus is provided with a buffer and accompanying circuitry for retrieving instruction code at a branch target address and providing that code to an execution unit within a single clock, much more quickly than the one bus cycle which has been required previously. Not only branches, but also interrupts may be handled with this relatively simple hardware, making the invention useful in the control field, among other applications. The buffer circuitry can store a plurality of branch target addresses and/or interrupt addresses.

Abstract: A stand-by control circuit includes a power ON detecting circuit which supplies a flag with a power ON detecting signal to be reset. In a testing mode, the power ON detecting circuit shuts off a current flowing therethrough, so that testing of LSIs each including the stand-by control circuit can be carried out without errors.

Abstract: A microprocessor having two different modes of operation includes a mode flag which designates one of the two operation modes of the microprocessor, and a central processing unit which executes a program in one of the two operation modes designated by the mode flag. The central processing unit includes a microprogram memory which stores an interrupt initiation microprogram, an output device which is responsive to an interrupt request for reading out the interrupt initiation microprogram from the microprogram memory and a circuit for executing the interrupt initiation microprogram to generate a sampling signal. A mode terminal is provided, which is supplied with operation mode information. A circuit responsive to the sampling signal samples a logic level of the operation mode information at the mode terminal. A circuit is provided, which is responsive to the sampled logic level from the sampling circuit in order to bring the mode flag into one of set and reset states of the mode flag designation.

Abstract: An industrial measuring apparatus comprises first and second sensors having identical measuring characteristics and arranged close to each other and also close to a common subject of measurement, for measuring the same parameter, a transmitting unit having an adder and a first subtracter respectively connected the sensors through amplifiers, and a receiving unit having a second subtracter connected to the adder and the first subtracter through two transmission lines and constituting a noise canceling device in cooperation with the adder and the first subtracter. The second subtracter produces a receiving signal by subtracting the output of the subtracter representing the difference between the outputs of the first and second sensors from the output of the adder representing the sum of the outputs of the two sensors.

Abstract: A display control apparatus having an improved attribute function is disclosed. The control apparatus comprises a refresh memory having a plurality of storage addresses, each storage address storing a pattern code and an attribute code, an address circuit for selecting one of the storage addresses of the refresh memory and a video signal generator for generating a video signal in accordance with the pattern code and the attribute code, and features an attribute memory for storing a control code and a control circuit for making the attribute code from the refresh memory effective or ineffective in accordance with the content of the control code.