Abstract: According to One embodiment, a semiconductor memory device includes: a first memory cell array; a second memory cell array arranged above the memory cell array; a third memory cell array arranged adjacent to the first memory cell array; a fourth memory cell array arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first word line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array and the third memory cell array.

Abstract: A semiconductor memory device includes first, second, and third chips. The first chip includes a first memory cell. The second chip includes a second memory cell. The third chip includes a row decoder and a sense amplifier. The first and second memory cells are commonly connected to the row decoder via a first word line. The first and second memory cells are connected to the sense amplifier via first and second bit lines, respectively. The sense amplifier includes a first node selectively connectable to the first and second bit lines. The sense amplifier is configured to sense a voltage at the first node to read data in the first memory cell when the first node is connected to the first bit line and sense the voltage at the first node to read data in the second memory cell when the first node is connected to the second bit line.

Abstract: According to one embodiment, a semiconductor memory device includes a first string unit including a first memory string including a first selection transistor and a first memory cell coupled to the first selection transistor, a second string unit including a second memory string including a second selection transistor and a second memory cell coupled to the second selection transistor, a first select gate line, a second select gate line, a first bit line, a second bit line, and a first word line. Both of the first select gate line and the second select gate line are selected in a first read operation. The first select gate line is selected and the second select gate line is not selected in a second read operation.

Abstract: In one embodiment, a semiconductor storage device includes a string that has one end electrically connected to a bit line, and another end electrically connected to a source line, and includes a plurality of memory cells. An operation of writing data to each of a plurality of adjacent first memory cells among the plurality of memory cells is sequentially performed in a direction from a first memory cell on a side of the source line to a first memory cell on a side of the bit line. An operation of reading data from each of the plurality of adjacent first memory cells is performed to allow a current to flow through the string in a first direction from the source line to the bit line.

Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

Abstract: A semiconductor memory device includes a memory chip. The memory chip includes a first region including a plurality of first memory cells and second memory cells, a second region different from the first region, a plurality of first word lines stacked apart from each other in a first direction in the first and second regions, a first pillar including a first semiconductor layer extending through the first word lines, and a first insulator layer provided between the first semiconductor layer and the first word lines, in the first region, the first memory cells being located at intersections of the first pillar with the first word lines, a first bonding pad in the second region, and a first transistor between the first word lines and the first bonding pad, and connected between one of the first word lines and the first bonding pad, in the second region.

Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.

Abstract: According to one embodiment, a semiconductor memory device includes first and second memory cells; a first word line connected to the first and second memory cells; a first bit line connected to the first memory cell; a second bit line connected to the second memory cell; a first sense amplifier connected to the first bit line; a second sense amplifier connected to the second bit line; a voltage generation circuit; and a first row decoder which supplies a voltage to the first word line.

Abstract: A semiconductor memory device including a substrate having a first region and a second region; a plurality of first transistors provided in the first region; a plurality of second transistors provided in the second region, the plurality of second transistors being electrically coupled to the plurality of first transistors, respectively, and a breakdown-voltage of the second transistor being lower than a breakdown-voltage of the first transistor. A plurality of joint metals are provided above the first region, the plurality of joint metals being electrically coupled to the plurality of first transistors, respectively. A plurality of bit lines are provided in an upper layer of the plurality of joint metals, the plurality of bit lines being coupled to the plurality of joint metals, respectively; and a plurality of memory cells are provided in an upper layer of the plurality of bit lines, the plurality of memory cells being coupled to the plurality of bit lines, respectively.

Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a first circuit which controls the plurality of bit lines according to first data, a source line commonly connected to first ends of the plurality of bit lines, and a second circuit which is connected to the source line and which detects second data according to a current amount in the source line.

Abstract: A memory device includes a first memory cell provided above a substrate; a first bit line coupled to the first memory cell and extending in a first direction; a first sense amplifier configured to sense a voltage of the first bit line; a second memory cell provided above the substrate; a second bit line adjacent to the first bit line and extending in the first direction, the second bit line being coupled to the second memory cell; a second sense amplifier configured to sense a voltage of the second bit line; and a third memory cell provided above the substrate. A third bit line not adjacent to the second bit line extends in the first direction, and is coupled to the third memory cell; and a third sense amplifier is configured to sense a voltage of the third bit line. The first and second sense amplifiers belong to a first sense amplifier group, are adjacent to each other and are arranged in a second direction intersecting the first direction.

Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

Abstract: A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.

Abstract: According to one embodiment, a memory system includes a memory controller configured to send a first command set including arithmetic operation target data and an address that designates a memory cell to store weight data; and a nonvolatile semiconductor memory configured to receive the first command set from the memory controller, read the weight data from the memory cell designated by the address, perform an arithmetic operation based on the arithmetic operation target data and the weight data, and send arithmetic operation result data to the memory controller.

Abstract: According to one embodiment, a semiconductor memory device includes a first bit line extending in a first direction and coupled to a first memory cell, a first pad coupled to the first bit line, a first sense amplifier coupled to the first pad, a second bit line being adjacent to the first bit line and extending in the first direction and coupled to a second memory cell, a second pad coupled to the second bit line, and a second sense amplifier coupled to the second pad. The first and second sense amplifiers are adjacent to each other and are arranged in a second direction intersecting the first direction. The first and second pads are adjacent to each other and are arranged in a third direction intersecting the first direction and the second direction.

Abstract: A semiconductor memory device according to an embodiment includes a substrate, a first memory cell, a first bit line, a first word line, a first transistor, and a second transistor. The first memory cell is provided above the substrate. The first bit line extends in a first direction. The first bit line is coupled to the first memory cell. The first word line extends in a second direction intersecting the first direction. The first word line is coupled to the first memory cell. The first transistor is provided on the substrate. The first transistor is coupled to the first bit line. The second transistor is provided below the first memory cell and on the substrate. The second transistor is coupled to the first word line.

Abstract: A semiconductor memory device comprises a first chip and a second chip bonded via bonding electrodes. The first chip comprises a semiconductor substrate. The second chip comprises: first conductive layers; semiconductor layers facing the first conductive layers; a first wiring layer including bit lines; a second wiring layer including wirings; and a third wiring layer including first bonding electrodes. The wirings each comprise: a first portion provided in a region overlapping one of the bit lines, and is electrically connected to the one of the bit lines; and a second portion provided in a region overlapping one of the first bonding electrodes, and is connected to the one of the first bonding electrodes. At least some of these wirings comprise a third portion connected to one end portion in a second direction of the first portion and one end portion in the second direction of the second portion.

Abstract: A first conductor extends along first and second axes. A first memory pillar is provided in the first conductor and includes a first semiconductor and a charge accumulation layer. A second conductor extends along the second axis and is in contact with the first memory pillar. A third conductor extends along the first and second axes and is arranged with a distance from the first conductor along the second axis. A second memory pillar is provided in the third conductor and includes a second semiconductor and a charge accumulation layer. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is coupled to the first and second memory pillars.