Abstract: A nonvolatile semiconductor memory includes a first memory string, a first interconnect coupled to one end of the first memory string, a second interconnect coupled to another end of the first memory string, a first circuit configured to control the first interconnect in accordance with first data, and a second circuit coupled to the second interconnect, the second circuit including a current mirror circuit, and the second circuit being configured to output second data based on an amount of a current flowing through the second interconnect.

Abstract: A memory device includes a first memory cell and a second memory cell each corresponding to a first column address, a first sense amplifier unit, a first bit line connected between the first memory cell and the first sense amplifier unit, and a second bit line connected between the second memory cell and the first sense amplifier unit.

Abstract: A semiconductor device includes plural storage portions, plural wirings each extending in a first direction, plural circuits each configured to sense a voltage of a respective one of the plural wirings, and plural pads each provided between one of the wirings and a corresponding one of the circuits. A first circuit and a second circuit among the plural circuits belong to a first group, are adjacent to each other, and are arranged in a second direction intersecting the first direction. A third circuit among the plural circuits belongs to a second group. The first group and the second group are adjacent to each other and arranged in the first direction. The plural pads are adjacent to each other and are arranged in the first direction or a third direction intersecting the first direction and the second direction.

Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

Abstract: A memory device includes a first memory cell and a second memory cell each corresponding to a first column address, a first sense amplifier unit, a first bit line connected between the first memory cell and the first sense amplifier unit, and a second bit line connected between the second memory cell and the first sense amplifier unit.

Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.

Abstract: A nonvolatile semiconductor memory includes a plurality of memory cells, a plurality of bit lines connected to the plurality of memory cells, a first circuit which controls the plurality of bit lines according to first data, a source line commonly connected to first ends of the plurality of bit lines, and a second circuit which is connected to the source line and which detects second data according to a current amount in the source line.

Abstract: A first conductor extends along first and second axes. A first memory pillar is provided in the first conductor and includes a first semiconductor and a charge accumulation layer. A second conductor extends along the second axis and is in contact with the first memory pillar. A third conductor extends along the first and second axes and is arranged with a distance from the first conductor along the second axis. A second memory pillar is provided in the third conductor and includes a second semiconductor and a charge accumulation layer. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is coupled to the first and second memory pillars.

Abstract: A memory device includes a first memory cell provided above a substrate; a first bit line coupled to the first memory cell and extending in a first direction; a first sense amplifier configured to sense a voltage of the first bit line; a second memory cell provided above the substrate; a second bit line adjacent to the first bit line and extending in the first direction, the second bit line being coupled to the second memory cell; a second sense amplifier configured to sense a voltage of the second bit line; and a third memory cell provided above the substrate. A third bit line not adjacent to the second bit line extends in the first direction, and is coupled to the third memory cell; and a third sense amplifier is configured to sense a voltage of the third bit line. The first and second sense amplifiers belong to a first sense amplifier group, are adjacent to each other and are arranged in a second direction intersecting the first direction.

Abstract: A memory device according to one embodiment includes includes bit lines, strings, first and second wirings, a word line, and a sequencer. Each of the strings has one end coupled to the bit lines. Each of the strings includes a memory cell, and first and second transistors coupled in series. The first wiring is coupled to the first transistor of each of the strings. The second wiring is coupled to the second transistor of each of the strings. The word line is coupled to the memory cell of each of the strings. The sequencer is configured to, in a read operation of N bytes in which the word line is selected, apply a first voltage to one of the first wiring line and the second wiring line, and apply a second voltage higher than the first voltage to the other of the first wiring line and the second wiring line.

Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.

Abstract: According to one embodiment, a memory device includes: a first chip including a first memory cell array; a second chip in contact with the first chip and including a second memory cell array; and a third chip in contact with the second chip and including a control circuit. The first memory cell array includes first and second transistors coupled in series. The second memory cell array includes third and fourth transistors coupled in series. The control circuit includes: fifth, sixth, and seventh transistors respectively having first ends coupled to gates of the first, third, and second and fourth transistors; a first decoder configured to switch a state of the fifth transistor; and a second decoder configured to switch a state of the sixth transistor independently of the state of the fifth transistor.

Abstract: A first conductor extends along first and second axes. A first memory pillar is provided in the first conductor and includes a first semiconductor and a charge accumulation layer. A second conductor extends along the second axis and is in contact with the first memory pillar. A third conductor extends along the first and second axes and is arranged with a distance from the first conductor along the second axis. A second memory pillar is provided in the third conductor and includes a second semiconductor and a charge accumulation layer. The fourth conductor extends along the second axis and is in contact with the second memory pillar. The fifth conductor extends along the second axis and is coupled to the first and second memory pillars.

Abstract: According to one embodiment, a semiconductor memory device includes a memory cell, a first voltage generator and a second voltage generator. The memory cell is provided above a substrate. The first voltage generator is provided between the substrate and the memory cell. The first voltage generator is configured to generate a first voltage to be supplied to the memory cell. The second voltage generator is provided between the substrate and the memory cell. The second voltage generator is configured to generate the first voltage and have a circuit configuration equivalent to the first voltage generator.

Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.

Abstract: According to one embodiment, a semiconductor memory device includes, a first string in which a first selection transistor, a first memory cell, and a second selection transistor are coupled in series, a second string in which a third selection transistor, a second memory cell, and a fourth selection transistor are coupled in series, a word line, a first selection gate line, a second selection gate line, a third selection gate line, a fourth selection gate line, a first bit line, and a second bit line. In a read operation of the first memory cell, when a voltage of the word line is raised to a first voltage, a second voltage is applied to the first bit line and a third voltage higher than the second voltage is applied to the second bit line.

Abstract: According to one embodiment, a semiconductor memory device includes: a first memory cell array; a second memory cell array arranged above the first memory cell array; a third memory cell array arranged adjacent to the first memory cell array; a fourth memory cell array arranged above the third memory cell array and arranged adjacent to the second memory cell array; a first word line coupled to the first memory cell array and the second memory cell array; a second word line coupled to the third memory cell array and the fourth memory cell array; a first bit line coupled to the first memory cell array and the fourth memory cell array; and a second bit line coupled to the second memory cell array and the third memory cell array.

Abstract: According to one embodiment, a memory device includes a substrate, a memory layer, and a circuit layer. The memory layer includes first to third regions arranged in a first direction. The circuit layer includes first and second transfer regions, and first and second sense amplifier regions. The first and second transfer regions are shifted in the first direction and arranged in a second direction. In a third direction, the first sense amplifier region overlaps the first region, and the second sense amplifier region overlaps the second region. The first sense amplifier region and the first transfer region are arranged in the first direction, and the second sense amplifier region and the second transfer region are arranged in the first direction.

Abstract: A semiconductor storage device includes word lines extending in first and second directions, and separated from each other in a third direction, sense amplifier circuits that partially overlap the word lines in the third direction, memory strings intersecting the word lines and extending in the third direction, memory-side bit lines extending in the first direction, separated from each other in the second direction, and including first and second adjacent memory-side bit lines, circuit-side bit lines between the word lines and the sense amplifier circuits and partially overlapping the respective memory-side bit lines in the third direction, and contact plugs extending in the third direction and respectively connecting the memory-side bit lines and the circuit-side bit lines. The contact plugs include first and second contract plugs that are electrically connected to the first and second memory-side bit lines, respectively, and are not aligned along the first or second direction.