Patents by Inventor Hiroshi Maejima

Hiroshi Maejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device
    Patent number: 10037813
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least four threshold voltages, a first bit line, a word line, and a first sense amplifier which is connected to the first bit line. The first sense amplifier applies a charging voltage to the first bit line in a first verification operation in which a first voltage is applied to the word line, does not apply the charging voltage to the first bit line in a second verification operation in which a second voltage higher than the first voltage is applied to the word line, and applies the charging voltage to the first bit line BL in a third verification operation in which a third voltage higher than the second voltage is applied to the word line.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: July 31, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Maejima, Noboru Shibata
  • THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY
    Publication number: 20180197612
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Application
    Filed: March 9, 2018
    Publication date: July 12, 2018
    Applicant: Toshiba Memory Corporation
    Inventor: Hiroshi MAEJIMA
  • Semiconductor storage device
    Patent number: 10014054
    Abstract: According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part.
    Type: Grant
    Filed: May 1, 2017
    Date of Patent: July 3, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Maejima
  • MEMORY DEVICE TO EXECUTE READ OPERATION USING READ TARGET VOLTAGE
    Publication number: 20180182464
    Abstract: A memory device includes first and second memory strings, first and second word lines and a controller. The first memory string includes first and second memory cells, a first select transistor, a second select transistor, and a third select transistor between the first and second memory cells. The second memory string includes third and fourth memory cells, a fourth select transistor above the third memory cell, a fifth select transistor below the fourth memory cell, and a sixth select transistor between the third and fourth memory cells. The first word line is electrically connected to gates of the first and third memory cells. The second word line is electrically connected to gates of the second and fourth memory cells. The controller is configured to execute a read operation on one of the memory cells, the read operation including a first phase and a second phase after the first phase.
    Type: Application
    Filed: February 22, 2018
    Publication date: June 28, 2018
    Inventor: Hiroshi MAEJIMA
  • Semiconductor memory device
    Patent number: 10008269
    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
    Type: Grant
    Filed: April 26, 2017
    Date of Patent: June 26, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Semiconductor memory device
    Patent number: 10002671
    Abstract: A semiconductor memory device includes first and second memory cell arrays, and first and second control circuits configured to execute an operation on the first and second memory cell arrays. The first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device. The second control circuit executes an operation on the second memory cell array responsive to second and third command sets that are received by the semiconductor memory device while the first control circuit is executing the operation on the first memory cell array.
    Type: Grant
    Filed: March 2, 2017
    Date of Patent: June 19, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Takahiro Shimizu, Noboru Shibata, Hiroshi Maejima
  • Semiconductor memory device
    Patent number: 9984761
    Abstract: A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.
    Type: Grant
    Filed: August 10, 2016
    Date of Patent: May 29, 2018
    Assignee: Toshiba Memory Corporation
    Inventors: Hiroshi Maejima, Koji Hosono, Tadashi Yasufuku, Noboru Shibata
  • Memory performing write operation in which a string transistor channel voltage is boosted before applying a program voltage to a word line
    Patent number: 9953708
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Grant
    Filed: December 2, 2016
    Date of Patent: April 24, 2018
    Assignee: TOSHIBA MEMORY CORPORATION
    Inventor: Hiroshi Maejima
  • Memory device that performs sensing operation during a bit line pre-charge operation to determine adjustment to the bit line charging voltage
    Patent number: 9941013
    Abstract: A memory device includes memory cells, word lines that are each connected to gates of a plurality of the memory cells, bit lines that are each connected to a plurality of the memory cells, and a control circuit configured to perform a determination operation on the memory cells. During the determination operation for a first memory cell among the memory cells, a first bit line connected to the first memory cell is charged using a bit line charge voltage, and the bit line charge voltage is adjusted based on a result of a first sensing operation that is performed on the first bit line. A second sensing operation is performed on the first bit line after the first sensing operation to determine whether a threshold voltage of the first memory cell is greater than a reference voltage.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: April 10, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • MEMORY DEVICE TO EXECUTED READ OPERATION USING READ TARGET VOLTAGE
    Publication number: 20180082753
    Abstract: A memory device includes a first string including first and second memory cells, first and second select transistors, and a third select transistor between the first and second select transistors, a second string including third and fourth memory cells, fourth and fifth select transistors, and a sixth select transistor between the fourth and fifth select transistors, and a controller. During a first read phase, a first voltage is applied to first, second, and third select transistors, and one of fourth and fifth select transistor, and a second voltage lower than the first voltage is applied to sixth select transistor and other of fourth and fifth select transistors. During a second read phase, the second voltage is applied to fourth, fifth, and sixth select transistors, and a read target voltage is applied to a selected word line.
    Type: Application
    Filed: March 1, 2017
    Publication date: March 22, 2018
    Inventor: Hiroshi MAEJIMA
  • Memory device to executed read operation using read target voltage
    Patent number: 9922717
    Abstract: A memory device includes a first string including first and second memory cells, first and second select transistors, and a third select transistor between the first and second select transistors, a second string including third and fourth memory cells, fourth and fifth select transistors, and a sixth select transistor between the fourth and fifth select transistors, and a controller. During a first read phase, a first voltage is applied to first, second, and third select transistors, and one of fourth and fifth select transistor, and a second voltage lower than the first voltage is applied to sixth select transistor and other of fourth and fifth select transistors. During a second read phase, the second voltage is applied to fourth, fifth, and sixth select transistors, and a read target voltage is applied to a selected word line.
    Type: Grant
    Filed: March 1, 2017
    Date of Patent: March 20, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20180075912
    Abstract: A semiconductor memory device includes first and second memory cell arrays, and first and second control circuits configured to execute an operation on the first and second memory cell arrays. The first control circuit executes an operation on the first memory cell array responsive to a first command set that is received by the semiconductor memory device. The second control circuit executes an operation on the second memory cell array responsive to second and third command sets that are received by the semiconductor memory device while the first control circuit is executing the operation on the first memory cell array.
    Type: Application
    Filed: March 2, 2017
    Publication date: March 15, 2018
    Inventors: Takahiro SHIMIZU, Noboru SHIBATA, Hiroshi MAEJIMA
  • SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER
    Publication number: 20180039428
    Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.
    Type: Application
    Filed: October 3, 2017
    Publication date: February 8, 2018
    Inventor: Hiroshi MAEJIMA
  • Memory system with non-volatile memory device that is capable of single or simulataneous multiple word line selection
    Patent number: 9865351
    Abstract: A memory system includes a memory device including a memory cell array having a first region of multiple first memory cells and a second region of multiple second memory cells, first word lines each connected to a gate of one of the first memory cells, and second word lines each connected to a gate of one of the second memory cells, and a controller configured to control an operation of the memory device. The memory device selects one word line when reading from or writing to the first memory cells and selects more than one word line when reading from or writing to the second memory cells.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: January 9, 2018
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Semiconductor memory device
    Patent number: 9824762
    Abstract: A semiconductor memory device includes a first memory block having a first memory cell transistor and a first select transistor, a second memory block having a second memory cell transistor and a second select transistor, a first select gate line that is electrically connected to a gate of the first select transistor, and a second select gate line that is electrically connected to a gate of the second select transistor. During writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period.
    Type: Grant
    Filed: January 3, 2017
    Date of Patent: November 21, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • Semiconductor storage device and controller
    Patent number: 9811270
    Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.
    Type: Grant
    Filed: October 28, 2016
    Date of Patent: November 7, 2017
    Assignee: Toshiba Memory Corporation
    Inventor: Hiroshi Maejima
  • MEMORY DEVICE
    Publication number: 20170271023
    Abstract: A memory device includes memory cells, word lines that are each connected to gates of a plurality of the memory cells, bit lines that are each connected to a plurality of the memory cells, and a control circuit configured to perform a determination operation on the memory cells. During the determination operation for a first memory cell among the memory cells, a first bit line connected to the first memory cell is charged using a bit line charge voltage, and the bit line charge voltage is adjusted based on a result of a first sensing operation that is performed on the first bit line. A second sensing operation is performed on the first bit line after the first sensing operation to determine whether a threshold voltage of the first memory cell is greater than a reference voltage.
    Type: Application
    Filed: September 29, 2016
    Publication date: September 21, 2017
    Inventor: Hiroshi MAEJIMA
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20170256316
    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
    Type: Application
    Filed: April 26, 2017
    Publication date: September 7, 2017
    Inventor: Hiroshi MAEJIMA
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20170236595
    Abstract: A semiconductor memory device includes a first memory cell which is capable of being set to any one of at least four threshold voltages, a first bit line, a word line, and a first sense amplifier which is connected to the first bit line. The first sense amplifier applies a charging voltage to the first bit line in a first verification operation in which a first voltage is applied to the word line, does not apply the charging voltage to the first bit line in a second verification operation in which a second voltage higher than the first voltage is applied to the word line, and applies the charging voltage to the first bit line BL in a third verification operation in which a third voltage higher than the second voltage is applied to the word line.
    Type: Application
    Filed: January 12, 2017
    Publication date: August 17, 2017
    Inventors: Hiroshi MAEJIMA, Noboru SHIBATA
  • SEMICONDUCTOR STORAGE DEVICE
    Publication number: 20170236586
    Abstract: According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part.
    Type: Application
    Filed: May 1, 2017
    Publication date: August 17, 2017
    Inventor: Hiroshi MAEJIMA