Patents by Inventor Hiroshi Maejima

Hiroshi Maejima has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Semiconductor memory device
    Patent number: 9711226
    Abstract: A semiconductor memory device includes a first well of a first conductivity type, a memory cell array including a plurality of memory cells stacked above the first well, the memory cells including a first memory cell transistor, a first wiring above the memory cells array and electrically connected to the first memory cell transistor, and a controller configured to execute an erase operation in which an erase voltage is applied to the first wiring while the first well is in an electrically floating state.
    Type: Grant
    Filed: February 26, 2016
    Date of Patent: July 18, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Semiconductor memory device
    Patent number: 9704584
    Abstract: A semiconductor memory device includes a first block including a first memory string that includes a first memory cell and a first select transistor, a second block including a second memory string that includes a second memory cell and a second select transistor, a source line that is connected to the first memory string and the second memory string, and a controller that applies a source line voltage to the source line and a first voltage to a gate of the second select transistor during a program operation in which data is written to the first memory cell, the first voltage being greater than ground voltage and less than or equal to the source line voltage.
    Type: Grant
    Filed: March 3, 2016
    Date of Patent: July 11, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Maejima, Yuya Suzuki, Hidehiro Shiga, Tomonori Kurosawa
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20170178739
    Abstract: A semiconductor memory device includes first and second memory cells, each of which includes a charge storage layer, a first bit line that is connected to the first memory cell, and a second bit line that is connected to the second memory cell. A writing operation includes multiple loops of a programming operation and a verification operation, and first data is written in the first memory cell, and second data different from the first data is written in the second memory cell through the writing operation. In a first loop of the writing operation, a first voltage is applied to the first bit line and the second bit line is maintained in an electrically floating state during the programming operation, and a verification operation relating to the second data is not performed and a verification operation relating to the first data is performed.
    Type: Application
    Filed: August 10, 2016
    Publication date: June 22, 2017
    Inventors: Hiroshi MAEJIMA, Koji HOSONO, Tadashi YASUFUKU, Noboru SHIBATA
  • Semiconductor storage device
    Patent number: 9672927
    Abstract: According to one embodiment, a semiconductor storage device of an embodiment of the present disclosure is provided with peripheral circuits, a memory cell array, upper bit lines, and first and second connecting parts. The memory cell array is disposed above the peripheral circuit, and includes at least first and second regions. The upper bit lines extend in a first direction and are above the memory cell array. The first and second connecting parts are respectively provided with contact plugs, and one of these connecting parts is formed between first and second regions. The upper bit lines includes a first group of upper bit lines which are connected to the peripheral circuits via the first connecting part, and a second group of upper bit lines which are connected to the peripheral circuits via the second connecting part.
    Type: Grant
    Filed: June 30, 2015
    Date of Patent: June 6, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Semiconductor memory in which source line voltage is applied during a read operation
    Patent number: 9672929
    Abstract: A semiconductor memory device includes a memory cell, a word line electrically connected to a gate of the memory cell, and a source line electrically connected to a first end of the memory cell. During a read operation of the memory cell, a first voltage is applied to the source line in a first operation to determine whether or not a threshold voltage of the memory cell is above a first threshold value, a second voltage is applied to the source line in a second operation to determine whether or not the threshold voltage of the memory cell is above a second threshold value, and a third voltage is applied to the source line in a third operation to determine whether or not the threshold voltage of the memory cell is above a third threshold value.
    Type: Grant
    Filed: June 6, 2016
    Date of Patent: June 6, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Semiconductor memory device
    Patent number: 9666296
    Abstract: A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
    Type: Grant
    Filed: August 8, 2016
    Date of Patent: May 30, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20170117047
    Abstract: A semiconductor memory device includes a first memory block having a first memory cell transistor and a first select transistor, a second memory block having a second memory cell transistor and a second select transistor, a first select gate line that is electrically connected to a gate of the first select transistor, and a second select gate line that is electrically connected to a gate of the second select transistor. During writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period.
    Type: Application
    Filed: January 3, 2017
    Publication date: April 27, 2017
    Inventor: Hiroshi MAEJIMA
  • THREE DIMENSIONAL STACKED NONVOLATILE SEMICONDUCTOR MEMORY
    Publication number: 20170084338
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Application
    Filed: December 2, 2016
    Publication date: March 23, 2017
    Applicant: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi MAEJIMA
  • MEMORY SYSTEM
    Publication number: 20170075595
    Abstract: A memory system includes a memory device including a memory cell array having a first region of multiple first memory cells and a second region of multiple second memory cells, first word lines each connected to a gate of one of the first memory cells, and second word lines each connected to a gate of one of the second memory cells, and a controller configured to control an operation of the memory device. The memory device selects one word line when reading from or writing to the first memory cells and selects more than one word line when reading from or writing to the second memory cells.
    Type: Application
    Filed: June 7, 2016
    Publication date: March 16, 2017
    Inventor: Hiroshi MAEJIMA
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20170069394
    Abstract: A semiconductor memory device includes a memory cell, a word line electrically connected to a gate of the memory cell, and a source line electrically connected to a first end of the memory cell. During a read operation of the memory cell, a first voltage is applied to the source line in a first operation to determine whether or not a threshold voltage of the memory cell is above a first threshold value, a second voltage is applied to the source line in a second operation to determine whether or not the threshold voltage of the memory cell is above a second threshold value, and a third voltage is applied to the source line in a third operation to determine whether or not the threshold voltage of the memory cell is above a third threshold value.
    Type: Application
    Filed: June 6, 2016
    Publication date: March 9, 2017
    Inventor: Hiroshi MAEJIMA
  • SEMICONDUCTOR STORAGE DEVICE AND CONTROLLER
    Publication number: 20170046078
    Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, first and second blocks, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in a first block, after a select gate line connected to the gate of a select transistor of one of the memory strings in the first block is selected, the data are sequentially written in the memory cells in the memory string connected to the selected select gate line. When data are written in the second block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the second block which have their control gates connected to the selected word line.
    Type: Application
    Filed: October 28, 2016
    Publication date: February 16, 2017
    Inventor: Hiroshi MAEJIMA
  • Semiconductor memory device
    Patent number: 9570180
    Abstract: A semiconductor memory device includes a first memory block having a first memory cell transistor and a first select transistor, a second memory block having a second memory cell transistor and a second select transistor, a first select gate line that is electrically connected to a gate of the first select transistor, and a second select gate line that is electrically connected to a gate of the second select transistor. During writing of data to a memory cell transistor in the first block, a first voltage is applied to the first select gate line during a first time period, a second voltage is applied to the second select gate line during a second time period after the first time period, and a third voltage lower than the first voltage is applied to the first select gate line during a third time period after the second time period.
    Type: Grant
    Filed: February 23, 2016
    Date of Patent: February 14, 2017
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Write controlling method for memory
    Patent number: 9558833
    Abstract: A three dimensional stacked nonvolatile semiconductor memory according to an example of the present invention includes a memory cell array comprised of first and second blocks. The first block has a first cell unit which includes a memory cell to be programmed and a second cell unit which does not include a memory cell to be programmed, and programming is executed by applying a program potential or a transfer potential to word lines in the first block after the initial potential of channels of the memory cells in the first and second cell units is set to a plus potential. In the programming, the program potential and the transfer potential are not applied to word lines in the second block.
    Type: Grant
    Filed: January 13, 2016
    Date of Patent: January 31, 2017
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventor: Hiroshi Maejima
  • Semiconductor memory device
    Patent number: 9524787
    Abstract: A semiconductor memory device includes memory cells, word lines that are electrically connected to gates of the memory cells, a source line that is electrically connected to one end of the memory cells, and a controller that executes a read operation over first, second, third, and fourth time periods. A first voltage is applied to a selected word line during the first and second time periods of the first operation, and a second voltage that is higher than the first voltage is applied to the selected word line during the third and fourth time periods of the second operation. A third voltage is applied to the source line during the first and third time periods, and fourth and fifth voltages that are lower than the third voltage are applied to the source line during the second and fourth time periods, respectively.
    Type: Grant
    Filed: March 4, 2016
    Date of Patent: December 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Semiconductor memory device
    Patent number: 9524789
    Abstract: A semiconductor memory device includes a memory cell, a sense amplifier electrically connected to the memory cell, the sense amplifier including a node for sensing a voltage during a sense operation and a data latch electrically connected to the node and configured to hold a first voltage corresponding to a voltage of the node when a strobe signal is issued during a strobe operation, and a controller configured to raise the voltage of the node during the strobe operation before the strobe signal is issued.
    Type: Grant
    Filed: March 17, 2016
    Date of Patent: December 20, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Semiconductor storage device and controller
    Patent number: 9514825
    Abstract: A semiconductor storage device includes memory cells, select transistors, memory strings, a block, word lines, and select gate lines. In the memory string, the current paths of plural memory cells are connected in series. When data are written in the block, after a word line connected to the control gates of memory cells of different memory strings in the second block is selected, the data are sequentially written in the memory cells of the different memory strings in the block which have their control gates connected to the selected word line.
    Type: Grant
    Filed: August 24, 2015
    Date of Patent: December 6, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Semiconductor memory device including circuits with data holding capability and bus for data transmission
    Patent number: 9472296
    Abstract: A semiconductor memory device includes a sense amplifier, and the sense amplifier includes a bus, first and second latch circuits, and a third transistor. The first latch circuit includes a first transistor connected to the bus, and the second latch circuit includes a second transistor connected to the bus. When data is transmitted from the first latch circuit to the second latch circuit, a third transistor is switched on to precharge the bus by applying a first voltage that is lower than a power source voltage of the first and second latch circuits to a gate of the third transistor. Thereafter, second and third voltages that are lower than the power source voltage are applied to gates of first and second transistors, respectively.
    Type: Grant
    Filed: September 4, 2015
    Date of Patent: October 18, 2016
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Hiroshi Maejima
  • Nonvolatile semiconductor memory device
    Patent number: 9460794
    Abstract: In a writing operation, a control circuit raises the voltage of a writing-prohibited bit line among a plurality of bit lines to a first voltage, and thereafter brings the writing-prohibited bit line into a floating state. Then, the control circuit raises the voltage of a writing bit line other than the writing-prohibited bit line to a second voltage. In this way, the control circuit prohibits writing into a memory transistor corresponding to the writing-prohibited bit line. On the other hand, the control circuit executes writing into a memory transistor corresponding to the writing bit line.
    Type: Grant
    Filed: October 6, 2014
    Date of Patent: October 4, 2016
    Assignee: KABUSHIKI KAISHA TOSHIBA
    Inventors: Hiroshi Maejima, Koji Hosono
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20160276034
    Abstract: A semiconductor memory device includes memory cells, word lines that are electrically connected to gates of the memory cells, a source line that is electrically connected to one end of the memory cells, and a controller that executes a read operation over first, second, third, and fourth time periods. A first voltage is applied to a selected word line during the first and second time periods of the first operation, and a second voltage that is higher than the first voltage is applied to the selected word line during the third and fourth time periods of the second operation. A third voltage is applied to the source line during the first and third time periods, and fourth and fifth voltages that are lower than the third voltage are applied to the source line during the second and fourth time periods, respectively.
    Type: Application
    Filed: March 4, 2016
    Publication date: September 22, 2016
    Inventor: Hiroshi MAEJIMA
  • SEMICONDUCTOR MEMORY DEVICE
    Publication number: 20160267992
    Abstract: A semiconductor memory device includes a first block including a first memory string that includes a first memory cell and a first select transistor, a second block including a second memory string that includes a second memory cell and a second select transistor, a source line that is connected to the first memory string and the second memory string, and a controller that applies a source line voltage to the source line and a first voltage to a gate of the second select transistor during a program operation in which data is written to the first memory cell, the first voltage being greater than ground voltage and less than or equal to the source line voltage.
    Type: Application
    Filed: March 3, 2016
    Publication date: September 15, 2016
    Inventors: Hiroshi MAEJIMA, Yuya SUZUKI, Hidehiro SHIGA, Tomonori KUROSAWA