Abstract: A swallowing sensor device includes a sensor unit comprising a sensor and a device that wirelessly transmits information detected by the sensor and a board group formed by stacking a plurality of rigid boards. The board group includes a fist rigid board on which one part of the sensor unit is mounted, a second rigid board on which other part of the sensor unit except for the one part of the sensor unit is mounted, and a third rigid board being disposed between the first rigid board and the second rigid board and comprising a through-hole drilled thereon, the through-hole being configured to electrically connecting the one part and the other part.

Abstract: A detecting system includes a sensor and a receiving device. The sensor is introduced into a living body through a mouth of the living body, transmits time-point related information associated with a plurality of time points different from one another, detects a physical amount in the living body, and transmits detection information representing the detected physical amount at each of the plurality of time points. The receiving device receives the time-point related information transmitted by the sensor and is on standby for receiving the detection information transmitted by the sensor on the basis of the plurality of time points associated with the received time-point related information.

Abstract: An ultrasound device generates polar-coordinate image data divided up into an (N×M) array of polar-coordinate image data blocks; a first external memory configured to store the (N×M) array of data blocks; a second external memory configured to store x-y coordinate image data corresponding to the polar-coordinate image data; a video processing chip comprising an internal memory configured to store an (N×R) array of the polar-coordinate image data blocks; and a controller configured to perform a data conversion operation on the (N×R) array of data blocks to generate x-y coordinate image data, and to store the x-y coordinate image data to the second external memory. N, M, and R are integers greater than 1; R is less than M; and an internal access time for the internal memory element is shorter than an external access time for the first external memory element.

Abstract: An ultrasound device generates polar-coordinate image data divided up into an (N×M) array of polar-coordinate image data blocks; a first external memory configured to store the (N×M) array of data blocks; a second external memory configured to store x-y coordinate image data corresponding to the polar-coordinate image data; a video processing chip comprising an internal memory configured to store an (N×R) array of the polar-coordinate image data blocks; and a controller configured to perform a data conversion operation on the (N×R) array of data blocks to generate x-y coordinate image data, and to store the x-y coordinate image data to the second external memory. N, M, and R are integers greater than 1; R is less than M; and an internal access time for the internal memory element is shorter than an external access time for the first external memory element.

Abstract: The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is performed at low speed, and that can fully exploit processibility, by means of input line memory 23 and output line memory 24, which can store image data of one scan line, and are arranged in the input unit and output unit, respectively; the input image data are written in input line memory 23 at the speed of the input image data; the image data that have been written to the input line memory are read at a speed n times faster than the input image data and are sent to processing unit 25 or memory unit 26; processing unit 25 and memory unit 26 receive the image data of one scan line at a speed n times faster than the speed of the input image data, perform a prescribed processing, and then output the processing results at a speed n times faster than the speed of the input image data; the image data output from processing unit 25 or memory unit 26 are selected

Abstract: The objective of the invention is to improve the processing efficiency of a system that repeatedly executes one instruction over multiple clock cycles. The SVP core 12 of this SVP (Scan-line Video Processor) 10 is made up of a three layer construction of the data input register (DIR) 16, the SIMD type digital signal processing unit 18, and the data output register (DOR) 20. The SIMD type digital signal processing unit 18 comprises a parallel arranged (connected) number of processing elements (PE0 to PEN−1) (for example, 864 units) equal to the number of pixels N on one horizontal scan line. The instruction generator (IG) 14, because the SVP core 12 operates as an SIMD parallel processor, internally houses a RAM or ROM program memory that holds the desired program.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: The objective of the invention is to provide an image processing device that can operate at high speed even if input/output with respect to the outside is performed at low speed, and that can fully exploit processibility, by means of input line memory 23 and output line memory 24, which can store image data of one scan line, and are arranged in the input unit and output unit, respectively; the input image data are written in input line memory 23 at the speed of the input image data; the image data that have been written to the input line memory are read at a speed n times faster than the input image data and are sent to processing unit 25 or memory unit 26; processing unit 25 and memory unit 26 receive the image data of one scan line at a speed n times faster than the speed of the input image data, perform a prescribed processing, and then output the processing results at a speed n times faster than the speed of the input image data; the image data output from processing unit 25 or memory unit 26 are selected

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including 8 plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single port memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: The decrypting device of this invention includes: a decrypting key generation circuit for generating a decrypting key based on first decrypting key information and second decrypting key information; and a decrypting circuit for decrypting encrypted information using the decrypting key, wherein the first decrypting key information is input from outside the decrypting device, and the second decrypting key information is stored inside the decrypting device.

Abstract: The television receiver including a display device capable of displaying a video signal having a predetermined display former of this invention includes; a plurality of video signal sources; a selection circuit for selecting one of a plurality of video signals output from the plurality of video signal sources; and an image processor for converting a format of the video signal selected by the selection circuit into the predetermined display format, wherein a video signal output from the processor is supplied to the display device.

Abstract: A memory interface device of the present invention includes: an input buffer including a plurality of input areas; an output buffer including a plurality of output areas; and a control section for controlling the input buffer, the output buffer and a single port memory. The control section controls the input buffer and the single port memory so as to transfer a signal stored in one of the input areas of the input buffer to the single port memory while storing an input signal in another one of the input areas of the input buffer. The control section controls the output buffer and the single part memory so as to output as an output signal a signal stored in one of the output areas of the output buffer while transferring a signal stored in the single port memory to another one of the output areas of the output buffer.

Abstract: A method for loading of program data with high speed and efficiency along with eliminating the need for software modification even if changes occur in the storage addresses and data length of the program data stored in the program memory. In order to load program data in a rewritable manner into a number of functional circuits FC0, FC1, . . . , FCn operating in accordance with the supplied program data, a program memory, for example, a ROM 10, a program loader 12, and program designating apparatus, for example, a microprocessor 14, are provided in the system.

Abstract: A single-instruction multiple-data (SIMD) processor (10) that incorporates features for horizontal scaling of video data. The processor (10) has a data input register (11) that is operable to store input data word in sequential locations in the data input register (11) and transfer the input data words to an array of processing elements. The processor (10) also has an output data register (16) operable to receive data output words from the array of processing elements and to output said data output words from sequential locations of said output data array. An input skip signal input to the processor causes a sequential data write operation to skip a location of the input data register while an output skip signal to the processor causes a sequential data read operation to skip a location of the output data register.

Abstract: A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.

Abstract: A synchronous vector processor (SVP) device (102) has a plurality of processing elements (150) which are comprised of an RF1 register (166), an ALU (164) and an RF0 (158). The processing elements are operable to be disposed between the data input register DIR (154) and the data output register (DOR) (168) to process data therebetween. Data is received in DIR (154), transferred to the processing elements (150), processed and then output to the DOR (168). A fast response clock operates the DIR (154) such that the jitter on the input signal is tracked. The Read clock on the DOR (168) is a stable clock. Data transferred between the DIR (154) and the DOR (168) is buffered in an elastic buffer to provide a time based compensation (TBC). To facilitate this, a buffer is implemented in either the RF1 (168) or the RF0 (158). A dual global rotation pointer is provided to generate two pointers that are asynchronous.

Abstract: A timing and control circuit and method for a synchronous vector processor (SVP) device having a plurality of one-bit processor elements organized in a linear array. This circuit includes a master controller circuit, a vertical timing generator circuit, a constant generator circuit, a horizontal timing generator circuit and an instruction generator circuit.

Abstract: A synchronous vector processor (SVP) (30) is provided to realize a horizontal decimation filter by processing in input value through a plurality of parallel processing elements (40). A plurality of input pixel values (80) representing a horizontal line of information in a video display are input to a data input register (DIR) (31) of the SVP (30). Each of the processing elements (40) is associated with a filter output and is operable to perform all calculations necessary to realize a multi-tap filter structure for the associated output. This is achieved by first increasing the frequency of the input signal by inserting zeros therein and then performing a number of multiplications and additions to generate an output value for that processing element, this realizing an interpolation FIR filter algorithm. The finite impulse response (FIR) filter algorithm is defined by predetermined filter coefficients stored in a constant generator (71d).

Abstract: A Serial Video Processor (SVP) is provided for processing data through a plurality of parallel processing elements (228). Data is first stored in a data input register (DIR) (222) and then processed through the PE (228). The data is then output into a Data Output Register (DOR) (230). During one pass of data through the PE (228), a variable is calculated and stored in an auxiliary register (242). This auxiliary value is typically selected from one of the processing elements representing a value over the entire or part of the input vector of data. A multiplexer (248) selects this value from the output value stored in the register (242) and then inputs it to a second multiplexer (240). The second multiplexer (240) is operable to select either a predefined variable from either another auxiliary register (238) or from an instruction generator ROM (236), or select the precalculated variable stored in the register (242).