Patents by Inventor Hiroshi Naruse

Hiroshi Naruse has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7307107
    Abstract: A photopolymerizable composition comprising a polymerizable compound and a photopolymerization initiator, wherein the polymerizable compound is characterized by comprising (a) a bifunctional (meth)acrylic acid (thio)ester compound containing a sulfur atom in the molecule and (b) at least one of a (meth)acrylic acid ester compound represented by the general formula (1) or a bifunctional (meth)acrylic acid ester compound having a urethane linkage: wherein R1 and R2 are each independently a hydrogen atom or a methyl group; R3 and R4 are each independently an alkyl group, an aralkyl group, an aryl group or a halogen atom; m and n are each an integer of 0 to 2; X1 is an alkylidene group having 1 to 3 carbon atoms; and Y1 and Y2 are each independently a poly(oxyalkylene) group with the proviso that at least one of Y1 and Y2 is a poly(oxyalkylene) group having a hydroxy group.
    Type: Grant
    Filed: July 17, 2003
    Date of Patent: December 11, 2007
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Masao Imai, Mitsuo Nakamura, Hiroshi Naruse, Osamu Kohgo, Masahiro Enna, Atsuo Otsuji
  • Publication number: 20070191615
    Abstract: The present invention is to provide a polymerizable compound which can be a raw material for a resin having high transparency, good heat resistance and mechanical strength required for optical components such as plastic lenses and the like, while attaining a high refractive index (nd) exceeding 1.7, and an optical component composed of such a resin. Disclosed is a compound represented by the general formula (3), wherein, in the formula, M represents a metal atom; X1 and X2 each independently represent a sulfur atom or an oxygen atom; R1 represents a divalent organic group; m represents an integer of 0 or 1 or more; p represents an integer of from 1 to n; q represents an integer of from 1 to (n-p); n represents a valence of a metal atom M; Yq each independently represent an inorganic or organic residue; and when q is 2 or more, Yq may be bonded to one another for forming a ring structure with the intermediary of a metal atom M.
    Type: Application
    Filed: March 31, 2005
    Publication date: August 16, 2007
    Applicant: MITSUI CHEMICALS, INC.
    Inventors: Atsuo Otsuji, Hiroshi Naruse, Mitsuo Nakamura
  • Patent number: 7224003
    Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.
    Type: Grant
    Filed: March 24, 2006
    Date of Patent: May 29, 2007
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
  • Publication number: 20060163684
    Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.
    Type: Application
    Filed: March 24, 2006
    Publication date: July 27, 2006
    Inventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
  • Patent number: 7042061
    Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.
    Type: Grant
    Filed: December 5, 2003
    Date of Patent: May 9, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
  • Publication number: 20060003261
    Abstract: A photopolymerizable composition comprising a polymerizable compound and a photopolymerization initiator, wherein the polymerizable compound is characterized by comprising (a) a bifunctional (meth)acrylic acid (thio)ester compound containing a sulfur atom in the molecule and (b) at least one of a (meth)acrylic acid ester compound represented by the general formula (1) or a bifunctional (meth)acrylic acid ester compound having a urethane linkage: wherein R1 and R2 are each independently a hydrogen atom or a methyl group; R3 and R4 are each independently an alkyl group, an aralkyl group, an aryl group or a halogen atom; m and n are each an integer of 0 to 2; X1 is an alkylidene group having 1 to 3 carbon atoms; and Y1 and Y2 are each independently a poly(oxyalkylene) group with the proviso that at least one of Y1 and Y2 is a poly(oxyalkylene) group having a hydroxy group.
    Type: Application
    Filed: July 17, 2003
    Publication date: January 5, 2006
    Applicant: Mitsui Chemicals, Inc.
    Inventors: Masao Imai, Mitsuo Nakamura, Hiroshi Naruse, Osamu Kohgo, Masahiro Enna, Atsuo Otsuji
  • Publication number: 20040231558
    Abstract: Aqueous ink which contains compounds having one or more structures represented by general formula (1) in a molecule or salts thereof and which has a clear hue and is excellent in light fastness and moisture resistance is provided.
    Type: Application
    Filed: March 25, 2004
    Publication date: November 25, 2004
    Inventors: Osamu Kohgo, Hiroshi Naruse, Kenichi Fujii, Tsutami Misawa, Akira Ogiso, Yasunori Saito, Rihoko Suzuki
  • Patent number: 6758890
    Abstract: Aqueous ink for ink jet recording comprising a coloring matter and an aqueous medium, in which at least one of dyes represented by the formula (A) or a salt thereof is contained as the coloring matter wherein R1 and R3, independently from each other, represent a hydrogen atom, an optionally substituted alkyl group, an optionally substituted alkoxy group, an amino group, a hydroxyl group or a halogen atom, R2 and R4, independently from each other, represent a hydrogen atom, an optionally substituted alkyl group, an optionally substituted aryl group or an aralkyl group, A represents an optionally substituted phenyl group or naphthyl group, X represents a divalent bonding group free from a saturated carbon ring, and m and n, independently from each other, represent an integer of 1 to 4.
    Type: Grant
    Filed: March 15, 2002
    Date of Patent: July 6, 2004
    Assignee: Mitsui Chemicals, Inc.
    Inventors: Yoriaki Matsuzaki, Kenichi Fujii, Osamu Kohgo, Hiroshi Naruse, Tsutami Misawa
  • Publication number: 20040108502
    Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.
    Type: Application
    Filed: December 5, 2003
    Publication date: June 10, 2004
    Inventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
  • Patent number: 6690423
    Abstract: The present invention provides a solid-state image pickup apparatus which is able to easily discharge signal charges in a signal accumulating section and which is free from reduction in the dynamic range of the element, thermal noise in a dark state, an image-lag and so forth even if the pixel size of the MOS solid-state image pickup apparatus is reduced, the voltage of a reading gate is lowered and the concentration in the well is raised. The solid-state image pickup apparatus according to the present invention incorporates a p-type silicon substrate having a surface on which a p+ diffusion layer for constituting a photoelectric conversion region and a drain of a reading MOS field effect transistor are formed. A signal accumulating section formed by an n-type diffusion layer is formed below the p+ diffusion layer. A gate electrode of the MOS field effect transistor is, on the surface of the substrate, formed between the p+ diffusion layer and the drain.
    Type: Grant
    Filed: March 19, 1999
    Date of Patent: February 10, 2004
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Nobuo Nakamura, Hisanori Ihara, Ikuko Inoue, Hidenori Shibata, Akiko Nomachi, Yoshiyuki Shioyama, Hidetoshi Nozaki, Masako Hori, Akira Makabe, Hiroshi Naruse, Hideki Inokuma, Seigo Abe, Hirofumi Yamashita, Tetsuya Yamaguchi
  • Publication number: 20030079648
    Abstract: Aqueous ink for ink jet recording comprising a coloring matter and an aqueous medium as main components, in which at least one of dyes represented by the formula (A) or their salts is contained as the coloring matter.
    Type: Application
    Filed: March 15, 2002
    Publication date: May 1, 2003
    Inventors: Yoriaki Matsuzaki, Kenichi Fujii, Osamu Kohgo, Hiroshi Naruse, Tsutami Misawa
  • Patent number: 6551882
    Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.
    Type: Grant
    Filed: March 27, 2001
    Date of Patent: April 22, 2003
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akiko Nomachi, Hiroshi Takato, Tadaomi Sakurai, Hiroshi Naruse, Koichi Kokubun, Hideaki Harakawa
  • Patent number: 6339237
    Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: January 15, 2002
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Akiko Nomachi, Hiroshi Takato, Tadaomi Sakurai, Hiroshi Naruse, Koichi Kokubun, Hideaki Harakawa
  • Publication number: 20010050768
    Abstract: The output light from a light source 10 is incident upon an optical fiber to be measured via an optical directional coupler 11, an optical switch 12, an optical amplifier 13, and an optical directional coupler 14. Light from the optical directional coupler 11 is incident upon a polarization controller 16. The output light from the polarization controller 16 and light returned from the optical fiber 15 are incident into an optical balance circuit 17, and these light are interfered. A fixed frequency, or alternatively a frequency which is varied stepwise, is output from a voltage control oscillator 18, according to a control signal from a DC voltage generation circuit 19 or from a saw tooth wave generation circuit 20. The output of the optical balance circuit 17 and the output of the voltage control oscillator 18 are mixed together by a mixer 26.
    Type: Application
    Filed: June 1, 2001
    Publication date: December 13, 2001
    Applicant: Ando Electric Co., Ltd
    Inventors: Haruyoshi Uchiyama, Yoshiyuki Sakairi, Hiroshige Ohno, Hiroshi Naruse
  • Publication number: 20010010390
    Abstract: In a MOS transistor of an LDD structure, a cobalt silicide film is formed in a region where adjacent gates are formed widely apart from each other, but is not formed in a region where adjacent gates are formed close to each other. The particular construction permits suppressing the leak current through the PN junction that is generated under the influence of the metal silicide compound in the region where adjacent gates are formed close to each other, and also permits ensuring the signal processing at a high speed in the region where adjacent gates are formed widely apart from each other.
    Type: Application
    Filed: March 27, 2001
    Publication date: August 2, 2001
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Akiko Nomachi, Hiroshi Takato, Tadaomi Sakurai, Hiroshi Naruse, Koichi Kokubun, Hideaki Harakawa
  • Patent number: 5963822
    Abstract: According to a method of fabricating a selective epitaxial film, a thin insulating film serving as a mask is formed on the entire surface of a semiconductor substrate having a (100) plane. An opening portion reaching the semiconductor substrate is formed in a desired region of the thin insulating film. An epitaxial film is selectively grown in the opening portion. The semiconductor substrate having the selective epitaxial film formed thereon is annealed at at least a pressure of 1,000 Pa and at least a temperature of 800.degree. C. to fill a gap on the contact surface between the thin insulating film and the selective epitaxial film.
    Type: Grant
    Filed: April 4, 1997
    Date of Patent: October 5, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Saihara, Hiroshi Naruse, Hiroyuki Sugaya
  • Patent number: 5926725
    Abstract: In a method of manufacturing a semiconductor device, to form an opening in an insulation film such as a silicon oxide on a semiconductor substrate in a reverse tapered sectional configuration such that no gap is formed between a side surface of an epitaxial growth layer formed in the opening and the opening in the insulation film, the insulation film having the opening is subjected to a thermal process in an atmosphere of non-oxidizing gas including hydrogen elements such as hydrogen, silane or disilane gas. An opening is formed in the insulation film on the semiconductor substrate using isotropic etching. As a result of the above-described thermal process, decomposition of a silicon oxide proceeds from the interface between the insulation film and the semiconductor substrate at a side-wall of the opening to eventually form the opening in a reverse tapered sectional configuration at least in an edge portion thereof.
    Type: Grant
    Filed: May 9, 1997
    Date of Patent: July 20, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hidenori Saihara, Hiroshi Naruse, Hiroyuki Sugaya, Shizue Hori
  • Patent number: 5877540
    Abstract: A semiconductor device. A semiconductor substrate has a first conductivity. A first insulating layer is on the semiconductor substrate and has an opening so that a portion of the semiconductor substrate is exposed. A semiconductor layer has a second conductivity on the portion. A region in said semiconductor layer prevents a leakage current caused by a minute defect and faceting.
    Type: Grant
    Filed: December 13, 1996
    Date of Patent: March 2, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroshi Naruse, Hiroyuki Sugaya, Hidenori Saihara, Yoshiro Baba
  • Patent number: 5864180
    Abstract: A semiconductor device and a method for manufacturing the same, in which a leak current generated in a pn junction formed between a silicon substrate and an epitaxial layer can be reduced. A silicon oxide film is formed on a silicon substrate having a (100) crystal plane. The silicon oxide film is patterned to form an opened portion and an inclined surface on a pattern edge of the silicon oxide film. The inclined surface forms an angle of 54.74.+-.5.degree. with the silicon substrate. An epitaxial layer is formed in the opened portion by selective epitaxial growth.
    Type: Grant
    Filed: February 24, 1998
    Date of Patent: January 26, 1999
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Shizue Hori, Yoshiro Baba, Hiroyuki Sugaya, Hiroshi Naruse
  • Patent number: 5733810
    Abstract: A groove is formed on a semiconductor substrate. A mask material layer is so formed on the surface of the semiconductor substrate as to open a groove region. With the mask material layer used as a mask, a semiconductor layer is selectively formed on the semiconductor substrate exposed with the inner wall surface of the groove. Then, the mask material layer is removed. An insulating film is formed on the semiconductor layer formed on the inner wall surface of the groove and the surface of the semiconductor substrate. The groove is buried with a conductor.
    Type: Grant
    Filed: March 19, 1997
    Date of Patent: March 31, 1998
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Yoshiro Baba, Hiroshi Naruse