Patents by Inventor Hiroshi Oishi

Hiroshi Oishi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240116615
    Abstract: A marine propulsion device that reduces white smoke generated during starting includes an engine, a crankshaft, a tilt angle sensor, and an ECU. The engine includes a cylinder, a piston inside the cylinder, and a connecting rod connected to the piston. The crankshaft is connected to the connecting rod. The tilt angle sensor is operable to detect a tilt state of the cylinder such that a first side portion thereof located on an opposite side from the crankshaft is lower than a second side portion thereof located on a same side as the crankshaft. The ECU is configured or programmed to execute a cranking control of a prolonged cranking time based on the tilt state of the cylinder and a stopped time of the engine.
    Type: Application
    Filed: July 12, 2023
    Publication date: April 11, 2024
    Inventors: Kimitaka SARUWATARI, Hiroshi SUZUKI, Masaya OISHI
  • Publication number: 20230286724
    Abstract: A packaging bag includes a cutting guide band extending along a transverse direction. The cutting guide band includes, a first guide band having first cut lines that are inclined at a predetermined angle with respect to the transverse direction; a second guide band having second cut lines that are inclined at a predetermined angle in a direction opposite a direction of the first cut lines with respect to the transverse direction; and a third guide band having third cut lines that are inclined at a predetermined angle in the same direction as the direction of the first cut lines with respect to the transverse direction. The cutting guide band has a fourth cut line between the first guide band and the second guide band and/or between the second guide band and the third guide band, the fourth cut line being perforated and extending along the transverse direction.
    Type: Application
    Filed: July 30, 2021
    Publication date: September 14, 2023
    Applicants: TOPPAN INC., HISAMITSU PHARMACEUTICAL CO., INC.
    Inventors: Kazuyoshi OKADA, Yoshikazu KUWANO, Hiroshi OISHI, Tetsuhiro KAWANO
  • Patent number: 11605716
    Abstract: The present invention provides a nitride semiconductor substrate suitable for a high frequency device. The nitride semiconductor substrate has a substrate, a buffer layer made of group 13 nitride semiconductors, and an active layer made of group 13 nitride semiconductors in this order, wherein the substrate is composed of a first substrate made of polycrystalline aluminum nitride, and a second substrate made of Si single crystal having a specific resistance of 100 ?·cm or more, formed on the first substrate, the average particle size of AlN constituting the first substrate is 3 to 9 ?m, and preferably, the second substrate grown by the MCZ method has an oxygen concentration of 1E+18 to 9E+18 atoms/cm3 and a specific resistance of 100 to 1000 ?·cm.
    Type: Grant
    Filed: November 11, 2020
    Date of Patent: March 14, 2023
    Assignee: COORSTEK KK
    Inventors: Hiroshi Oishi, Jun Komiyama, Yoshihisa Abe, Kenichi Eriguchi
  • Patent number: 11597033
    Abstract: A laser processing head includes a laser irradiation part, a collimating optical system for collimating laser light from the laser irradiation part, and a collecting optical system for collecting the laser light after passing through the collimating optical system. An optical system including the collimating optical system and the collecting optical system is configured such that the laser light after passing through the collecting optical system has coma aberration.
    Type: Grant
    Filed: March 23, 2018
    Date of Patent: March 7, 2023
    Assignee: PRIMETALS TECHNOLOGIES JAPAN, LTD.
    Inventors: Takahiro Yagi, Hiroshi Oishi, Ryosuke Mitsuoka
  • Publication number: 20220068614
    Abstract: The present invention relates to a semiconductor manufacturing member including a silicon carbide-containing boron carbide film at least on a surface thereof, in which the silicon carbide-containing boron carbide film has a content of silicon carbide of 5 wt % or more and 18 wt % or less and a balance being boron carbide.
    Type: Application
    Filed: August 23, 2021
    Publication date: March 3, 2022
    Inventors: Masahiko ICHISHIMA, Hiroshi OISHI, Noriko OMORI, Akira MIYAZAKI, Masahiro KUBOTA, Jun KOMIYAMA
  • Patent number: 11155219
    Abstract: There is provided a door trim including: an armrest; an ornament member coupled to the armrest; and a planar heater configured to warm the armrest or the ornament member. The planar heater is disposed between a resin core member and a surface member which form the armrest or the ornament member, and includes a nonwoven fabric and a heating wire fixed to the nonwoven fabric. The nonwoven fabric includes first and second bonded parts and a connection part connecting between the first and second bonded parts. The second bonded part is routed to be disposed on the back surface side of the armrest (the back surface side of the ornament member) by the connection part being inserted into an interface gap between the armrest and the ornament member. A thermostat is mounted on the second bonded part.
    Type: Grant
    Filed: September 27, 2017
    Date of Patent: October 26, 2021
    Assignee: KASAI KOGYO CO., LTD.
    Inventor: Hiroshi Oishi
  • Publication number: 20210184004
    Abstract: The present invention provides a nitride semiconductor substrate suitable for a high frequency device. The nitride semiconductor substrate has a substrate, a buffer layer made of group 13 nitride semiconductors, and an active layer made of group 13 nitride semiconductors in this order, wherein the substrate is composed of a first substrate made of polycrystalline aluminum nitride, and a second substrate made of Si single crystal having a specific resistance of 100 ?·cm or more, formed on the first substrate, the average particle size of AlN constituting the first substrate is 3 to 9 ?m, and preferably, the second substrate grown by the MCZ method has an oxygen concentration of 1E+18 to 9E+18 atoms/cm3 and a specific resistance of 100 to 1000 ?·cm.
    Type: Application
    Filed: November 11, 2020
    Publication date: June 17, 2021
    Applicant: CoorsTek KK
    Inventors: Hiroshi OISHI, Jun KOMIYAMA, Yoshihisa ABE, Kenichi ERIGUCHI
  • Publication number: 20210046582
    Abstract: A laser processing head includes a laser irradiation part, a collimating optical system for collimating laser light from the laser irradiation part, and a collecting optical system for collecting the laser light after passing through the collimating optical system. An optical system including the collimating optical system and the collecting optical system is configured such that the laser light after passing through the collecting optical system has coma aberration.
    Type: Application
    Filed: March 23, 2018
    Publication date: February 18, 2021
    Applicant: Primetals Technologies Japan, Ltd.
    Inventors: Takahiro YAGI, Hiroshi OISHI, Ryosuke MITSUOKA
  • Publication number: 20210039567
    Abstract: There is provided a door trim including: an armrest; an ornament member coupled to the armrest; and a planar heater configured to warm the armrest or the ornament member. The planar heater is disposed between a resin core member and a surface member which form the armrest or the ornament member, and includes a nonwoven fabric and a heating wire fixed to the nonwoven fabric. The nonwoven fabric includes first and second bonded parts and a connection part connecting between the first and second bonded parts. The second bonded part is routed to be disposed on the back surface side of the armrest (the back surface side of the ornament member) by the connection part being inserted into an interface gap between the armrest and the ornament member. A thermostat is mounted on the second bonded part.
    Type: Application
    Filed: September 27, 2017
    Publication date: February 11, 2021
    Inventor: Hiroshi OISHI
  • Patent number: 10559679
    Abstract: There is provided a nitride semiconductor epitaxial substrate having a channel layer, a spacer layer, and an electron supply layer that are stacked in this order. The channel layer is GaN. The spacer layer is AlaGa1-aN (0<a<0.5). The electron supply layer is AlxlnyGa1-x-yN (0<x+y?1). The spacer layer has a thickness of two molecular layers or less.
    Type: Grant
    Filed: August 17, 2018
    Date of Patent: February 11, 2020
    Assignee: COORSTEK KK
    Inventors: Hiroshi Oishi, Noriko Omori, Yoshihisa Abe
  • Publication number: 20190074369
    Abstract: There is provided a nitride semiconductor epitaxial substrate having a spacer structure capable of obtaining characteristics unprecedented in the prior art. In the nitride semiconductor epitaxial substrate of the present invention, a channel layer, a spacer layer, and an electron supply layer are stacked in this order. The channel layer is GaN. The spacer layer is AlaGa1?aN (0<a<0.5). The electron supply layer is AlxInyGa1?x?yN (0<x+y?1). The spacer layer has a thickness of two molecular layers or less. Thus, adverse effects due to the existence of a conventional spacer layer are suitably suppressed.
    Type: Application
    Filed: August 17, 2018
    Publication date: March 7, 2019
    Applicant: CoorsTek KK
    Inventors: Hiroshi OISHI, Noriko OMORI, Yoshihisa ABE
  • Patent number: 10068858
    Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.
    Type: Grant
    Filed: October 4, 2016
    Date of Patent: September 4, 2018
    Assignee: COORSTEK KK
    Inventors: Yoshihisa Abe, Kenichi Eriguchi, Noriko Omori, Hiroshi Oishi, Jun Komiyama
  • Publication number: 20180151714
    Abstract: Provided is a nitride semiconductor substrate which improves electron mobility and reduce a series resistance component of a transistor. In the nitride semiconductor substrate, an electron transit layer, an intermediate layer, and an electron supply layer are laminated in this order. The electron transit layer includes a nitride semiconductor of a first group 13 element. The intermediate layer and the electron supply layer each include a nitride semiconductor of the first group 13 element and a second group 13 element. The nitride semiconductor substrate has a profile in which an atomic ratio of the second group 13 element to a total of the first group 13 element and the second group 13 element increases in the thickness direction of the intermediate layer from an interface between the electron transit layer and the intermediate layer, and the atomic ratio decreases after a maximum peak value is obtained in the intermediate layer.
    Type: Application
    Filed: November 17, 2017
    Publication date: May 31, 2018
    Applicant: CoorsTek KK
    Inventors: Noriko OMORI, Hiroshi OISHI, Yoshihisa ABE, Jun KOMIYAMA
  • Patent number: 9748344
    Abstract: The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: August 29, 2017
    Assignee: COORSTEK KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi, Tomoko Watanabe
  • Publication number: 20170110414
    Abstract: A compound semiconductor substrate according to the present invention includes a compound semiconductor layer formed on one main surface of a ground substrate via a seed layer, wherein the ground substrate is formed of a sintered body, the seed layer is formed of a single crystal, the compound semiconductor layer includes a structure having a buffer layer and an active layer that are sequentially crystal-grown on the seed layer, a thermal expansion coefficient of the sintered body is 0.7 times or more and 1.4 times or less an average thermal expansion coefficient of the entire compound semiconductor layer, and an FWHM of an X-ray diffraction peak of the buffer layer obtained by an X-ray diffraction rocking curve measurement is 800 arcsec or less.
    Type: Application
    Filed: October 4, 2016
    Publication date: April 20, 2017
    Applicant: COORSTEK KK
    Inventors: Yoshihisa ABE, Kenichi ERIGUCHI, Noriko OMORI, Hiroshi OISHI, Jun KOMIYAMA
  • Publication number: 20170011919
    Abstract: The present invention provides a nitride semiconductor substrate having an initial nitride and a nitride semiconductor sequentially stacked on one principal plane of a base substrate, wherein the nitride semiconductor substrate comprises recesses depressed from an interface between the base substrate and the initial nitride toward the base substrate along one arbitrary cross section; the recesses each have a diameter of 6 nm or more and 60 nm or less and are formed at a density of 3×108 pieces/cm2 or more and 1×1011 pieces/cm2 or less; and the recess preferably has a depth of 3 nm or more and 45 nm or less from the interface between the base substrate and the initial nitride toward the base substrate.
    Type: Application
    Filed: July 6, 2016
    Publication date: January 12, 2017
    Applicant: CoorsTek KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi, Tomoko Watanabe
  • Patent number: 9536955
    Abstract: A nitride semiconductor substrate is provided which is suitable for a high withstand voltage power device and prevents a warp and a crack from generating in a Si substrate when forming a thick nitride semiconductor layer on the substrate. A nitride semiconductor substrate 1 is prepared in such a manner that a buffer layer 3 and a semiconductor active layer 4 each comprising a group 13 nitride are stacked one by one on one principal plane of a Si single crystal substrate, the one principal plane has an offset angle of 0.1° to 1° or ?1° to ?0.1° with respect to a (111) plane, an average dopant concentration in a bulk is 1×1018 to 1×1021 cm?3, the Si single crystal substrate 2 has a SiO2 film on the back, and the total thickness of the buffer layer 3 and the semiconductor active layer 4 is 4 to 10 ?m.
    Type: Grant
    Filed: April 22, 2014
    Date of Patent: January 3, 2017
    Assignee: COORSTEK KK
    Inventors: Jun Komiyama, Kenichi Eriguchi, Akira Yoshida, Hiroshi Oishi, Yoshihisa Abe, Shunichi Suzuki
  • Patent number: 9530846
    Abstract: A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary three places in a radial direction from a cross section cleaved in a diameter portion and observing an interface between the first layer and the nitride semiconductor layer by taking a width of at least 500 nm in the radial direction, a value is within the range of 6 nm or more and 15 nm or less in a mean value of the three places with regard to a difference between a maximum height of a convex top portion and a minimum height of a concave bottom portion of the first layer in a thickness direction from the single crystal substrate toward the nitride semiconductor layer. A value is 10 nm or more and 25 nm or less in the mean value.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: December 27, 2016
    Assignee: CoorsTek KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi
  • Publication number: 20160293710
    Abstract: A solution is formation of a nitride semiconductor layer on one principal plane of a single crystal substrate through a first layer. Upon selecting arbitrary three places in a radial direction from a cross section cleaved in a diameter portion and observing an interface between the first layer and the nitride semiconductor layer by taking a width of at least 500 nm in the radial direction, a value is within the range of 6 nm or more and 15 nm or less in a mean value of the three places with regard to a difference between a maximum height of a convex top portion and a minimum height of a concave bottom portion of the first layer in a thickness direction from the single crystal substrate toward the nitride semiconductor layer. A value is 10 nm or more and 25 nm or less in the mean value.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 6, 2016
    Applicant: CoorsTek KK
    Inventors: Noriko Omori, Hiroshi Oishi, Yoshihisa Abe, Jun Komiyama, Kenichi Eriguchi
  • Patent number: 9117743
    Abstract: A nitride semiconductor substrate suitable for a high withstand voltage power device is provided in which current collapse is controlled, while reducing leakage current. In a nitride semiconductor substrate, wherein a buffer layer, an active layer, and an electron supply layer, each comprising a group 13 nitride, are stacked one by one on a silicon single crystal substrate, the buffer layer has a structure where a multilayer stack in which a pair of nitride layers having different concentrations of Al or Ga are repeatedly deposited a plurality of times on an initial layer of AlxGa1?xN (0?x?1) is stacked, and includes a doping layer whose carbon concentration is 1×1018 to 1×1021 cm?3 and whose Si concentration is 1×1017 to 1×1020 cm?3, a thickness of the doping layer is 15% or more of the total thickness of the buffer layer.
    Type: Grant
    Filed: May 7, 2014
    Date of Patent: August 25, 2015
    Assignee: COVALENT MATERIALS CORPORTION
    Inventors: Jun Komiyama, Akira Yoshida, Hiroshi Oishi