Patents by Inventor Hiroshi Okano

Hiroshi Okano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110289955
    Abstract: A desiccant air conditioner has a high energy efficiency due to the absence of excessive heat loss due to ventilation. In order to meet this requirement, the desiccant air conditioner is equipped with a honeycomb rotor wash-coated with agents having capabilities of absorptions of humidity, carbon dioxide and nitrogen, and this honeycomb rotor is divided into at least an absorption zone and a desorption zone. The air in a room is, after being passed through the absorption zone, fed back to the room, and the air which is passed through the desorption zone is exhausted into outside of the room. In this way, carbon dioxide and nitrogen in a room, the latter quantity being corresponded to that of the consumed oxygen in the room, are exhausted into outside of the room, allowing to exhaust carbon dioxide and at the same time to keep the oxygen density to within an allowed limit without the need of excessive ventilation.
    Type: Application
    Filed: May 26, 2011
    Publication date: December 1, 2011
    Applicant: SEIBU-GIKEN CO., LTD.
    Inventor: Hiroshi Okano
  • Patent number: 8063692
    Abstract: A semiconductor integrated circuit includes: an internal circuit; a detecting circuit which detects an element characteristic of the internal circuit; a calculating circuit which calculates a first consumption energy consumed when a power gating operation is performed on a task processed by the internal circuit and a second consumption energy consumed when an operation of reducing a voltage and a frequency is performed in accordance with the element characteristic; and a switching circuit which performs the power gating operation on the internal circuit when the first consumption energy is smaller than the second consumption energy and performs the operation of reducing a voltage and a frequency when the second consumption energy is smaller than the first consumption energy.
    Type: Grant
    Filed: June 10, 2010
    Date of Patent: November 22, 2011
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Okano
  • Patent number: 8063509
    Abstract: A power supply voltage adjusting apparatus includes a voltage setting part that, according to a characteristic variation of a semiconductor integrated circuit, sets a first power supply voltage of a first power supply domain module among a plurality of modules in the semiconductor integrated circuit, each module respectively having a different power supply voltage; a detecting part that compares phases of a first clock signal flowing through the first power supply domain module and a second clock signal flowing through a second power supply domain module to detect a phase difference; and a voltage adjusting part that adjusts a second power supply voltage supplied to the second power supply domain module to reduce the phase difference detected by the detecting part.
    Type: Grant
    Filed: September 16, 2009
    Date of Patent: November 22, 2011
    Assignee: Fujitsu Limited
    Inventor: Hiroshi Okano
  • Patent number: 8008967
    Abstract: In a semiconductor integrated circuit including plural types of transistors having different threshold voltages, a plurality of oscillators including respective types of transistors are provided. The respective oscillation frequencies of these oscillators are counted, and based on the count values, a voltage to be set on a power supply voltage device for the semiconductor integrated circuit is determined according to the count values.
    Type: Grant
    Filed: March 19, 2008
    Date of Patent: August 30, 2011
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Okano, Atsuki Inoue
  • Publication number: 20100244942
    Abstract: A semiconductor integrated circuit includes: an internal circuit; a detecting circuit which detects an element characteristic of the internal circuit; a calculating circuit which calculates a first consumption energy consumed when a power gating operation is performed on a task processed by the internal circuit and a second consumption energy consumed when an operation of reducing a voltage and a frequency is performed in accordance with the element characteristic; and a switching circuit which performs the power gating operation on the internal circuit when the first consumption energy is smaller than the second consumption energy and performs the operation of reducing a voltage and a frequency when the second consumption energy is smaller than the first consumption energy.
    Type: Application
    Filed: June 10, 2010
    Publication date: September 30, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi OKANO
  • Patent number: 7753995
    Abstract: A revolving gas adsorption concentrator uses about 300 degree centigrade of hot desorption air. The revolving gas adsorption concentrator prevents leakage of such hot desorption air. An elastic seal which has elasticity divides a honeycomb shape rotor into a desorption zone and an adsorption zone and touches the honeycomb shape rotor. A heat-resistant seal comprises of material whose heat resistance is higher than elastic seal. The heat-resistant seal has two plates which has a mutually opened spacing to prevent hot gas from going to the elastic seal based on the labyrinth effectiveness. The elastic seal is formed in the outside of desorption zone from heat-resistant seal. The seal of the hot desorption air is almost blocked by heat-resistant seal and the desorption air which leaked slightly can be thoroughly blocked completely by elastic seal.
    Type: Grant
    Filed: December 11, 2007
    Date of Patent: July 13, 2010
    Assignee: Seibu Giken Co., Ltd.
    Inventors: Hiroshi Okano, Ken-ichiro Yamada
  • Publication number: 20100164286
    Abstract: A power supply voltage adjusting apparatus includes a voltage setting part that, according to a characteristic variation of a semiconductor integrated circuit, sets a first power supply voltage of a first power supply domain module among a plurality of modules in the semiconductor integrated circuit, each module respectively having a different power supply voltage; a detecting part that compares phases of a first clock signal flowing through the first power supply domain module and a second clock signal flowing through a second power supply domain module to detect a phase difference; and a voltage adjusting part that adjusts a second power supply voltage supplied to the second power supply domain module to reduce the phase difference detected by the detecting part.
    Type: Application
    Filed: September 16, 2009
    Publication date: July 1, 2010
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi OKANO
  • Publication number: 20090145301
    Abstract: A revolving gas adsorption concentrator uses about 300 degree centigrade of hot desorption air. The revolving gas adsorption concentrator prevents leakage of such hot desorption air. An elastic seal which has elasticity divides a honeycomb shape rotor into a desorption zone and an adsorption zone and touches the honeycomb shape rotor. A heat-resistant seal comprises of material whose heat resistance is higher than elastic seal. The heat-resistant seal has two plates which has a mutually opened spacing to prevent hot gas from going to the elastic seal based on the labyrinth effectiveness. The elastic seal is formed in the outside of desorption zone from heat-resistant seal. The seal of the hot desorption air is almost blocked by heat-resistant seal and the desorption air which leaked slightly can be thoroughly blocked completely by elastic seal.
    Type: Application
    Filed: December 11, 2007
    Publication date: June 11, 2009
    Applicant: SEIBU GIKEN CO., LTD.
    Inventors: Hiroshi Okano, Ken-ichiro Yamada
  • Publication number: 20080191681
    Abstract: In a semiconductor integrated circuit including plural types of transistors having different threshold voltages, a plurality of oscillators including respective types of transistors are provided. The respective oscillation frequencies of these oscillators are counted, and based on the count values, a voltage to be set on a power supply voltage device for the semiconductor integrated circuit is determined according to the count values.
    Type: Application
    Filed: March 19, 2008
    Publication date: August 14, 2008
    Applicant: Fujitsu Limited
    Inventors: Hiroshi OKANO, Atsuki Inoue
  • Patent number: 7221478
    Abstract: A digital image receiving apparatus includes a media drive (11) for reading image information from a storage medium (M1), an image information processing unit (22) for processing the image information to display a plurality of images in the image information read by the media drive, in thumbnail image form on a display (12), and an order information processing unit (24) for creating order information including which images to be printed from a printing order given by a customer for each image displayed on the display (12). The image information processing unit (22) includes an image data size acquisition unit (22a) for acquiring image data sizes of image data included in the image information and serving as printing sources. Information on the image data sizes acquired is displayed on the display (12) as associated with thumbnail images of corresponding image information.
    Type: Grant
    Filed: August 29, 2002
    Date of Patent: May 22, 2007
    Assignee: Noritsu Koki Co., Ltd.
    Inventors: Tetsuya Wada, Hiroshi Okano
  • Patent number: 7140001
    Abstract: A framework for a business application system, which is used for constructing the business application system, is described by an object-oriented language having characteristics of abstraction and inheritance. The framework includes an abstract class group 10 having abstractly defined the structure and behavior of the business application system, and a common component group 20 including a plurality of common components commonly for use in the business application system. The abstract class group 10 includes a system core class group 11 having abstractly defined the basic structure and behavior of the business application system, and a screen system class group 12, a report system class group 13 and a business logic system class group 14, which inherit the system core class group 11.
    Type: Grant
    Filed: March 5, 1999
    Date of Patent: November 21, 2006
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Mari Natori, Hiroshi Okano
  • Patent number: 7133973
    Abstract: An an address generator generates a read address. It is detected whether the generated read address is continuous to the read address previously generated. A cache unit control circuit controls the read data to be directly output to a requester of the read data without passing the read data through a cache RAM, if a cache miss occurs, and if it has been detected that the two addresses are continuous. As a result, the subsequent operations can executed even if the present operation has not been completed.
    Type: Grant
    Filed: January 31, 2003
    Date of Patent: November 7, 2006
    Assignee: Fujitsu Limited
    Inventors: Fumihiko Hayakawa, Hiroshi Okano
  • Patent number: 7134004
    Abstract: An information processing device reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing includes: an instruction reading request portion which assigns a read address to the instruction store portion, an instruction buffering portion which includes a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion. A branching instruction detection portion detects a branching instruction in the instruction sequence read from the instruction store portion. A branch target address information buffering portion includes a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target address of the branching instruction.
    Type: Grant
    Filed: September 20, 2000
    Date of Patent: November 7, 2006
    Assignee: Fujitsu Limited
    Inventors: Shin-ichiro Tago, Taizo Sato, Yoshimasa Takebe, Yasuhiro Yamazaki, Teruhiko Kamigata, Atsuhiro Suga, Hiroshi Okano, Hitoshi Yoda
  • Publication number: 20060224870
    Abstract: The present invention is defined in that an information processing device which reads, buffers, decodes and executes instructions from an instruction store portion by pipeline processing comprises: an instruction reading request portion which assigns a read address to the instruction store portion; an instruction buffering portion including a plurality of instruction buffers which buffer an instruction sequence read from the instruction store portion; an instruction execution unit which decodes and executes instructions buffered by the instruction buffering portion; a branching instruction detection portion which detects a branching instruction in the instruction sequence read from the instruction store portion; and a branch target address information buffering portion including a plurality of branch target address information buffers which, when the branching instruction detection portion has detected a branching instruction, buffer the branch target address information for generating the branch target addre
    Type: Application
    Filed: May 31, 2006
    Publication date: October 5, 2006
    Inventors: Shin-ichiro Tago, Taizo Sato, Yoshimasa Takebe, Yasuhiro Yamazaki, Teruhiko Kamigata, Atsuhiro Suga, Hiroshi Okano, Hitoshi Yoda
  • Patent number: 7096375
    Abstract: A circuit for data transfer includes a first buffer operating at a first clock frequency, a plurality of second buffers operating at a second clock frequency, and a selector circuit which receives data at the first clock frequency, and supplies the data to a selected one of the first buffer and the second buffers.
    Type: Grant
    Filed: November 19, 2002
    Date of Patent: August 22, 2006
    Assignee: Fujitsu Limited
    Inventors: Shigetoshi Wakayama, Hiroshi Okano, Yoshio Hirose
  • Patent number: 6931508
    Abstract: In an information processing device, a first address adder generates a first address representing a target for write of data or a storage location of data to be read. A second address adder generates a second address by adding 8 to the first address. First to seventh selectors appropriately select either the first address or the second address, and supply the selected address to first to seventh memory areas, respectively. An eighth memory area is supplied with the first address.
    Type: Grant
    Filed: December 13, 2002
    Date of Patent: August 16, 2005
    Assignee: Fujitsu Limited
    Inventors: Hiroshi Okano, Fumihiko Hayakawa
  • Patent number: 6868472
    Abstract: In a cache memory control method and computer of the present invention, a cache memory is connected to a main memory and divided into a plurality of cache blocks, and a lock/unlock signal is supplied to the cache memory to either set a replace-inhibition state of at least one of the cache blocks in which replacing at least one of the cache blocks to the main memory is inhibited, or reset the replace-inhibition state of at least one of the cache clocks such that replacing at least one of the cache block to the main memory is allowed. Either reading or writing of the main memory is performed by using the remaining cache blocks of the cache memory, other than the at least one of the cache blocks, such that, when the replace-inhibition state is set by the lock/unlock signal, replacing the at least one of the cache blocks to the main memory is inhibited during the reading or writing of the main memory.
    Type: Grant
    Filed: September 28, 2000
    Date of Patent: March 15, 2005
    Assignee: Fujitsu Limited
    Inventors: Hideo Miyake, Atsuhiro Suga, Yasuki Nakamura, Teruhiko Kamigata, Hitoshi Yoda, Hiroshi Okano, Yoshio Hirose
  • Publication number: 20040237540
    Abstract: A co-generation system and a dehumidification air-conditioner, which generates electricity and provides highly efficient air-conditioning by reducing the latent heat load of the air-conditioner. Exhaust gas from either a turbine or an internal combustion engine heats air for desorption of adsorbed moisture from a humidity rotor. The humidity rotor has a sound adsorption material to attenuate high frequency noise coming from the exhaust outlet of the co-generation system.
    Type: Application
    Filed: October 17, 2003
    Publication date: December 2, 2004
    Applicant: SEIBU GIKEN CO, LTD.
    Inventors: Hiroshi Okano, Yukito Kawakami, Mototsugu Nagamatsu
  • Patent number: 6815003
    Abstract: A method for fabricating an electrode for lithium secondary battery formed by depositing a thin film composed of active material capable of lithium storage and release, on a metallic foil to be used as a current collector, in which the surface of the metallic foil is roughened through wet-etching and then the thin film is deposited on the roughened surface.
    Type: Grant
    Filed: November 29, 2001
    Date of Patent: November 9, 2004
    Assignee: Sanyo Electric Co., Ltd.
    Inventors: Hiromasa Yagi, Koji Endo, Hisaki Tarui, Hiroshi Okano, Shingo Nakano
  • Publication number: 20040060036
    Abstract: There is provided an enterprise system constructing method capable of supporting to rapidly construct enterprise systems to share and reuse the whole structure of the systems, and of flexibly and easily changing and extending the systems.
    Type: Application
    Filed: September 15, 2003
    Publication date: March 25, 2004
    Applicant: Kabushiki Kaisha Toshiba
    Inventors: Mari Natori, Hiroshi Okano, Seiichiro Tanaka