Patents by Inventor Hiroshi Shigehara
Hiroshi Shigehara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9057623Abstract: A navigation device includes a road periphery display change unit 3 that selects a road R which connects to, intersects with, or is adjacent to a guidance route/a travel plan route 21 from a map database 5, and displays the road in a high contrast on the inside of a predetermined distance from the guidance route/the travel plan route 21, displays the road in a low contrast on the outside of the predetermined distance, and displays the road by changing continuously or stepwise a gradation in an intermediate region between the inside and the outside.Type: GrantFiled: May 23, 2011Date of Patent: June 16, 2015Assignee: MITSUBISHI ELECTRIC CORPORATIONInventors: Tsuyoshi Sempuku, Yoko Sano, Hiroshi Shigehara, Makoto Otsuru, Kotoyu Sasayama
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Publication number: 20120323487Abstract: A navigation device includes a road periphery display change unit 3 that selects a road R which connects to, intersects with, or is adjacent to a guidance route/a travel plan route 21 from a map database 5, and displays the road in a high contrast on the inside of a predetermined distance from the guidance route/the travel plan route 21, displays the road in a low contrast on the outside of the predetermined distance, and displays the road by changing continuously or stepwise a gradation in an intermediate region between the inside and the outside.Type: ApplicationFiled: May 23, 2011Publication date: December 20, 2012Inventors: Tsuyoshi Sempuku, Yoko Sano, Hiroshi Shigehara, Makoto Otsuru, Kotoyu Sasayama
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Patent number: 6462611Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor(N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.Type: GrantFiled: December 28, 2001Date of Patent: October 8, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa, Toshinobu Hisamoto
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Publication number: 20020053941Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.Type: ApplicationFiled: December 28, 2001Publication date: May 9, 2002Inventors: Hiroshi Shigehara, Masanori Kinugasa, Toshinobu Hisamoto
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Patent number: 6335653Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.Type: GrantFiled: October 31, 2000Date of Patent: January 1, 2002Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa, Toshinobu Hisamoto
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Patent number: 6288582Abstract: An output circuit for a semiconductor integrated circuit includes an output terminal, a first NMOS transistor having one end of a current path between a drain and a source thereof connected to a first node, having a control signal input a gate thereof, and having the other end of the current path connected to a ground potential node, a second NMOS transistor having one end of a current path between a drain and a source thereof connected to the first node and the other end connected to an output terminal, a PMOS transistor and an NMOS transistor connected between a second node that is a gate of the second NMOS transistor and the output terminal, to act as capacitance elements, and a pull-up element connected between the second node and the node of the power potential.Type: GrantFiled: September 21, 2000Date of Patent: September 11, 2001Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Shigehara
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Patent number: 6249146Abstract: Either the power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to the output terminal while an power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to the pn-junction provided between a drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.Type: GrantFiled: March 13, 2000Date of Patent: June 19, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
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Patent number: 6194952Abstract: When a power supply terminal (10) is grounded, a circuit (101) is in the OFF state, and a high potential is transferred from a circuit (3) to a bus line (BL), the high potential is transferred to a node (100) via the source of a transistor (P1), back gate (Nw), and transistor (P2). A NAND circuit (NA1) always outputs a control signal (VGP) of a level equal to the node (100) to the gate of the transistor (P1) to turn non-conductive the transistor (P1). Hence, a current path from a terminal (B) to a terminal (A) or from the terminal (B) to the back gate (Nw) is cut off to prevent wasteful current consumption.Type: GrantFiled: May 5, 1999Date of Patent: February 27, 2001Assignee: Kabushiki Kaisha ToshibaInventor: Hiroshi Shigehara
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Patent number: 6169443Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.Type: GrantFiled: November 9, 1999Date of Patent: January 2, 2001Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa, Toshinobu Hisamoto
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Patent number: 6097217Abstract: Either the power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.Type: GrantFiled: December 14, 1998Date of Patent: August 1, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
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Patent number: 6084431Abstract: In a case where a plurality of outputs are connected and used, even when a voltage higher than the power-supply voltages inside the integrated circuit is applied to the signal output terminal, the reliability of the internal elements is prevented from deteriorating. The semiconductor integrated circuit includes a PMOS transistor that has its source potentially isolated from its back gate and has one end of the current path between its source and drain connected via a transistor switch to the signal output terminal.Type: GrantFiled: November 27, 1996Date of Patent: July 4, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Yoshihiro Iwamoto
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Patent number: 6054736Abstract: A semiconductor device of the present invention comprises: a semiconductor substrate of a first conductive type; a gate electrode formed on the semiconductor substrate; a first semiconductor region of a second conductive type different from the first conductive type, the first semiconductor region being formed on the semiconductor substrate in one of both side regions of the gate electrode so as to be adjacent to the gate electrode; a second semiconductor region of the second conductive type formed on the semiconductor substrate in the other region of the both side regions of the gate electrode so as to be adjacent to the gate electrode; a third semiconductor region of the second conductive type formed in the one region so as to be isolated from the first semiconductor region and to be spaced from the second semiconductor region by a greater distance than that between the first and third semiconductor regions; a connecting portion for connecting the first semiconductor region to the third semiconductor regionType: GrantFiled: May 13, 1998Date of Patent: April 25, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa, Akira Takiba, Ryouichi Isohata
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Patent number: 6020778Abstract: Two terminals of each of transistors (P1, N1) are connected between two terminals (A, B). A body effect compensation circuit (COMP-P1) for the transistor (P1) and a body effect compensation circuit (COMP-N1) for the transistor (N1) are arranged. The back gates of transistors (P1P, P2P) in the circuit (COMP-P1) and transistors (P1N, P2N) in the circuit (COMP-N1) are commonly connected to the back gate of the transistor (P1). The back gates of transistors (N1N, N2N) in the circuit (COMP-N1) and transistors (N1P, N2P) in the circuit (COMP-P1) are commonly connected to the back gate of the transistor (N1). With this structure, in transferring a signal from one terminal (A or B) to the other terminal (B or A) or vice verse, the signal potential is transferred to the back gates of the transistors (P1, N1) at a high speed to increase the signal transfer speed.Type: GrantFiled: April 23, 1998Date of Patent: February 1, 2000Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa, Toshinobu Hisamoto
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Patent number: 5892387Abstract: In a situation where another analog switching circuit 502 outputs a high potential Vh, this high potential Vh is applied to an output terminal OUT1 of an analog switching circuit 504. When a ground potential is supplied to a node 10 with a changeover switch SW, a diode DD1 falls to an inversely biased state, whereby a potential at a backgate node Nw comes to be approximately equal to the potential Vh. Moreover, a potential approximately equal to the potential Vh is a power source terminal of an NAND gate NAND1, and it is transmitted to an output terminal VGP through an internal circuit, whereby a P channel MOS transistor P1 is turned off. Moreover, the output VGP from an inverter INV5 makes also an N channel MOS transistor N1 turn off. With such a constitution, an unnecessary current is prevented from flowing from a power source potential terminal on a bus line and so on to a ground potential terminal through a parasitic diode, thereby performing full-swinging without lowering an output level.Type: GrantFiled: July 15, 1997Date of Patent: April 6, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
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Patent number: 5880603Abstract: Either a power-supply potential or a ground potential is applied to a power-supply node through a switch. When a potential higher than the ground potential is applied to an output terminal while the power-supply node is connected to the ground-potential node, the potential of a back gate of a first PMOS transistor incorporated in an output section increases in accordance with the potential of the output terminal, due to a pn-junction provided between the drain and back gate of the first PMOS transistor. At this time, a second PMOS transistor whose source-drain path is connected between the back gate and gate of the first PMOS transistor is turned on, whereby the potential of the back gate of the first PMOS transistor is transferred to the gate thereof.Type: GrantFiled: May 31, 1996Date of Patent: March 9, 1999Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
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Patent number: 5841619Abstract: To an input terminal is connected one end of the source-to-drain current path of an NMOS the gate of which is connected to Vcc. The other end of the current path of the NMOS is connected by a protection circuit comprised of a PMOS and an NMOS to the common gates of a PMOS and an NMOS in the input stage of an internal circuit. In the protection circuit, the PMOS has its source and gate connected to Vcc and its drain connected to the common gates of the PMOS and the NMOS, while the NMOS has its source and gate connected to Vss and its drain connected to the common drains of the PMOS and the NMOS.Type: GrantFiled: December 5, 1995Date of Patent: November 24, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Yasunori Tanaka, Junya Masumi
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Patent number: 5831449Abstract: An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.Type: GrantFiled: April 21, 1997Date of Patent: November 3, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
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Patent number: 5825220Abstract: An auto-clear circuit which has a switch device connected between a power supply voltage terminal and first and second nodes, and a potential division device, connected between the first node and a ground terminal, for outputting a first potential obtained by dividing a potential of the first node. Also included is a charge/discharge device, connected between the second node and a ground terminal, for charging or discharging the second node on the basis of the first potential output from the potential division device, and a latch device for holding a potential of the second node to output a signal from an output terminal, and supplying the signal to the switch device to control an opening/closing operation.Type: GrantFiled: January 2, 1997Date of Patent: October 20, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Masanori Kinugasa, Hiroshi Shigehara, Akira Takiba
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Patent number: 5739702Abstract: The bus hold circuit comprises: an input stage inverter (IN1) connected between a first supply voltage (Vcc) terminal and a second supply voltage (Vss) terminal and including: a first P-channel transistor (P1); and a first N-channel transistor (N1) connected in series to the first P-channel transistor, a gate of the first P-channel transistor and a gate of the first N-channel transistor being connected in common to a bus line (INA); and an output stage inverter (IN2) also connected between the first supply voltage (Vcc) terminal and the second supply voltage (Vss) terminal and including: a second P-channel transistor (P4); a third P-channel transistor (P2) connected in series to the second P-channel transistor; and a second N-channel transistor (N2) connected in series to the third P-channel transistor, a gate of the second P-channel transistor (P4) being connected to the bus line (Lout), a gate of the third P-channel transistor (P2) and a gate of the second N-channel transistor (N2) being connected in commonType: GrantFiled: August 29, 1996Date of Patent: April 14, 1998Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa
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Patent number: 5661414Abstract: An output circuit comprising an output stage and a control signal generator. The output stage is constituted by a first P-channel MOS transistor and an N-channel MOS transistor. The control signal generator generates a signal for driving the Gates of the MOS transistors, it comprises a NAND gate, a NOR gate NOR1 and an inverter INV1. The first P-channel MOS transistor of the output stage has a source and a back gate which are isolated in terms of potential. A second P-channel MOS transistor is provided, whose source-drain path is connected between the back gate and gate of the first P-channel MOS transistor incorporated in the output stage.Type: GrantFiled: February 15, 1995Date of Patent: August 26, 1997Assignee: Kabushiki Kaisha ToshibaInventors: Hiroshi Shigehara, Masanori Kinugasa