Abstract: An output circuit according to the present invention comprises an input terminal, first and second MOS transistors of a same conductivity type connected in series between first and second power supplies to form a current path, and alternately turned on in response to an input signal from the input terminal, an output terminal connected to a connection point of the current path of the first and second MOS transistors, and a switching element having a current path one end of which is connected to the output terminal and another end of which is connected to a back gate of the first MOS transistor, for performing a switching operation in response to the input signal from the input terminal, the switching element preventing a parasitic diode generated between the back gate of the first MOS transistor and the first power supply from turning on, and controlling a potential of the back gate of the first MOS transistor.

Abstract: A transistor circuit comprises a MOS transistor with an open back gate, and control means for controlling a voltage to be applied to the control gate of the MOS transistor, whereby the control means controls the avalanche breakdown voltage of a parasitic bipolar transistor formed by the drain, back gate and source of the MOS transistor.

Abstract: A transistor circuit apparatus comprises a MOS transistor to be improved, for preventing an avalanche breakdown, the MOS transistor being connected in a channel conductor path provided between one of power supply terminals and a terminal of an output, a separate circuit connected to the output terminal and driven by a voltage from a separate power supply, and a pull-down unit including a second transistor connected between one of said power supply terminals and a back gate of the MOS transistor, the second transistor being turned on with an output node of the separate circuit used as power supply when the MOS transistor remains at a ground potential level with no power supply potential supplied, thereby pulling down the potential level of a back gate node of the MOS transistor to the level of one of the power supply terminals.

Abstract: An interface circuit includes first and second MOS transistors of depletion type, first and second switching elements, and a control circuit. The current path of the first MOS transistor is connected between an output node of a MOS circuit formed in a semiconductor substrate and an output terminal and the gate thereof is connected to a power supply. The first switching element is connected between the backgate of the first MOS transistor and a ground terminal. The second switching element and the current path of the second MOS transistor are serially connected between the backgate of the first MOS transistor and the output terminal. The gate of the second MOS transistor is connected to the power supply and the backgate thereof is connected to the backgate of the first MOS transistor. The first and second switching elements are set into complementary states according to an output of the MOS circuit in response to an output signal of the control circuit.

Abstract: An IC is divided into four circuit blocks. These four circuit blocks have the same function. While one of the circuit blocks is not functioning, a mode setting circuit generates mode control signals for selecting a mode in which the operation frequency of the circuit block is set lower than in a normal operation mode. A main control circuit controls the entire operation of the IC, and generates clock signals for defining the operations of the circuit blocks. Sub-control circuits are arranged so as to correspond to the circuit blocks and receive their respective mode control signals and clock signals. Upon receiving the mode control signals, the sub-control circuits controls their corresponding circuit blocks as to whether the circuit blocks are operated in the normal operation mode or at a frequency lower than that in the normal operation mode.

Abstract: This invention discloses a signal output circuit including DC and AC buffers having output nodes commonly connected to a signal output terminal, and an AC buffer control circuit for driving the AC buffer when an output from the DC buffer is changed and for controlling an output from the AC buffer in a high-impedance state when the output from the DC buffer is stationary.

Abstract: The source-drain paths of first and second N-channel MOS transistors are series-connected between a first node to which a first power source voltage is applied and a second node to which a ground voltage is applied. The gate of the first MOS transistor is supplied with an input signal and the gate of the second MOS transistor is supplied with a signal obtained by inverting the input signal by means of a CMOS inverter. The inverter is supplied with a second power source voltage which is independent from the first power source voltage as an operation power source voltage.

Abstract: An output buffer circuit includes a first output buffer having a high output resistance determined by DC specifications, a second output buffer having an output resistance satisfying AC specifications when simultaneously driven with the first output buffer, and a control circuit for controlling an operation of the second output buffer. An input signal is supplied to the input node of the first output buffer, and the output node of the first output buffer is connected to an output terminal. The output node of the second output buffer is connected to the output terminal. The control circuit is responsive to the potential of the input signal or of the output terminal to control the operation of the second output buffer. The control circuit drives the second output buffer when the output from the first output buffer is changed, and sets the output from the second output buffer in the high impedance state when the output from the first output buffer is stationary.

Abstract: A series circuit of two P-channel transistors and a series circuit of two N-channel transistors are used respectively as a latch circuit which temporarily latches an input signal until the power source fluctuation caused by the change of the output signal is suppressed. The gates of the transistors of the two series-circuits are supplied with the output signal of an output-stage circuit and a delayed output signal obtained by delaying the above output signal so that either one of the two series-circuits can be controlled to be turned on so as to temporarily latch an input signal in a dynamic manner until the power source fluctuation is suppressed. Since the gate signals to the transistors of the two series-circuits are directly supplied without being passed through single-channel type transfer gates, a sufficiently large bias voltages are supplied to the gate of the latch circuits even under the low power source voltage.

Abstract: A memory cell array stores data in its row and column directions. A counter counts clock signal pulses, represents the counted value by using binary system, and outputs, as the column address, values occupying predetermined lower bit positions, while supplying values occupying predetermined upper and lower bit positions into an adder circuit. The adder circuit processes the values supplied, and outputs, as the row address, the values thus processed, so that the memory cell array is accessed diagonally.

Abstract: An oscillation circuit having a clocked inverter operating during a predetermined period of time after the start of the oscillation. A feedback circuit is formed by the clocked inverter and another inverter at the start time of the oscillation. The oscillation circuit is therefore driven by a large amount of current and thus the oscillation start time can be shortened and the oscillation start voltage can be lowered. On the other hand, the oscillation circuit is driven only by the other inverter after starting the oscillation. Since a constant current source is inserted serially in the path of the power source of the other inverter. A constant operating current always flows through the other inverter without being affected by the variations of the threshold voltage of the transistors and the variations of the power source voltages. As a result, a low consumption current characteristic of the oscillation circuit can be obtained under low power source voltage.

Abstract: The source-drain paths of p-channel first and second MOSFETs are connected in series between a node, to which a high-potential power source voltage is supplied, and a signal output node. The source-drain paths of n-channel third and fourth MOSFETs are connected in series between the signal output node and a node to which a low-potential power source voltage is supplied. A signal from an input node is supplied to the gates of said four MOSFETs in a parallel manner. The source-drain path of an n-channel fifth MOSFET is connected in parallel to the source-drain path of the second MOSFET which is not directly connected to the node of the high-potential power source voltage. The gate of the fifth MOSFET is connected to the node of the high-potential power source voltage. The source-drain path of a p-channel sixth MOSFET is connected in parallel to the source-drain path of the third MOSFET which is not directly connected to the node of the low-potential power source voltage.

Abstract: Human speech is analyzed and a feature parameter is extracted from the human speech. The feature parameter is quantized and a quantization parameter is generated. Part of the bits of the quantization parameter is a predetermined bit pattern when the feature parameter is in a predetermined range. The part of the bits of the quantization parameter is tranformed into an additive parameter of at least one bit. The human speech is synthesized on the basis of the quantization parameter and the additive parameter. It is possible to nonlinearly quantize human speech into a quantization parameter having a small number of bits and to generate the synthesis parameter from the quantization parameter using a small size circuit.

Abstract: A pattern recognition apparatus is constituted by a feature data extraction section, a RAM for storing feature data, a memory for storing standard pattern data, an arithmetic section for performing a similarity measurement calculation between input pattern data and the standard pattern data, based on a multiple similarity method, and a controller for recognizing an input signal, based on the calculation result from the arithmetic section.

Abstract: A D/A converter, which has two output terminals, produces an estimated analog voltage signal from one output terminal which is connected to a comparator. The comparator compares the estimated analog voltage signal with an input analog voltage signal fed from an analog voltage signal source, thereby to produce a signal which corresponds to the difference in the respective values of the two intput analog voltage signals. The estimated analog voltage signal is output from the other output terminal of the D/A converter, which is connected to a load. The D/A converter can produce the analog voltage signal at either output terminal thereof.

Abstract: A multiplier multiplies first binary data X and second binary data Y in 2' complement format, X=(X4, X3, X2, X1) and Y=(Y4, Y3, Y2, Y1) to obtain the product Q=(Q4, Q3, Q2, Q1). An adder/subtractor performs addition/subtraction of third binary data Q'=(Q4, Q3, Q4, Q4) and fourth binary data Z=(Z4, Z3, Z2, Z1) in 2's complement format in response to a control signal. The third binary data includes upper bits and lower bits. The upper bits includes the upper two bits Q4 and Q3 of the multiplication result Q=(Q4, Q3, Q2, Q1). The lower two bits include the inverted most significant bit Q4 of the multiplication result. When the adder/subtractor operates in the adder mode, the inverted most significant bit Q4 of the multiplication result is applied as a carry input to the adder/subtractor. In the subtractor mode, the most significant bit Q4 of the multiplication result is applied as a carry bit to the adder/subtractor.

Abstract: Extension directions of source electrode layer and a drain electrode are parallel to rows or columns of an array of alternately arranged source regions and drain regions, thereby forming widths of source and drain electrode layers wider than those of a conventional transistor to obtain a large mutual conductance.

Abstract: A Pi generator receives the multiplier data Y and produces the Pi on the basis of the data Y2i, Y2i+1, and Y2i+2 of three continuous bits of the multiplier data Y (in which, it is defined that Pi=Y2i+Y2i+1-2.multidot.Y2i+2, Pi=Y2i+Y2i+1-2.multidot.Y2i+2' and Y0=0, and i=0, 1, . . . , n/2-1, and Yj is the bit data of the jth bit of the multiplier Y). A partial-product generator receives the Pi from the Pi generator and a multiplicand X, and obtains the partial products X.multidot.Pi of the multiplicand X and the Pi. A partial-product adding circuit weights 2.sup.2i to the partial products X.multidot.Pi derived by the partial-product generator, and adds the resultant data, thereby producing the negative product (-X.multidot.Y) of the multiplicand X and multiplier Y.

Abstract: An up/down counter device includes a D-type flip-flop circuit for producing a count signal of the 0th bit in synchronism with a clock signal, and 1st to n-th flip-flop circuits for producing count signals of the 1st to the n-th bits in synchronism with a clock signal. The first logic circuit is connected between the output of the D-type flip-flop circuit and the JK terminals of the first flip-flop circuit. The first stage logic circuit includes a first logic circuit section supplied with an up/down mode signal and the output signal of the D-type flip-flop circuit, and a second logic circuit connected in series with with the first logic circuit. Each of the 2nd to the n-th stage logic circuits includes a first logic circuit which is connected between the output terminal of the prestage flip-flop circuit and the JK terminals of the post stage flip-flop circuit, and a second logic circuit section connected to the first logic circuit.

Abstract: A speech synthesizing apparatus has a first memory storing a plurality of phrase data each including speech data, an address designating circuit for designating an address of the first memory, a second memory for storing synthesizing condition data, and a synthesizer for synthesizing a speech signal based on speech data from the first memory in accordance with the synthesizing condition data stored in the second memory. Each phrase data stored in the first memory also includes the corresponding synthesizing condition data. When each phrase data is read out from the first memory, the synthesizing condition data is first read out and is stored in the second memory, and then the speech data is read out and is supplied to the synthesizer.