Abstract: A solid electrolytic capacitor includes an anode element made of a valve action metal, a dielectric oxide film formed on a surface of the anode element, a solid electrolytic layer formed on a surface of the dielectric oxide film, and a cathode layer formed on a surface of the solid electrolytic layer. The solid electrolytic layer has an iron concentration not greater than 100 ppm. Alternatively or in combination therewith, a weight fraction of residues in the solid electrolytic layer is smaller than 5 wt %. The polymerization residue is an oxidizing agent and a monomer that is produced when such solid electrolytic layer is formed.

Abstract: A solid electrolytic capacitor comprising comprises a pair of electrodes, and a dielectric film provided between the paired electrodes wherein at least one of the paired electrodes comprising a first conductive polymer layer which is made of a polymer of a member selected from the group consisting of pyrrole and derivatives thereof, the first conductive polymer layer being doped with a mixed dopant of a polyvalent anion and a monovalent anion consisting of a sulfonate ion dissociated from an anionic surface active agent. The conductive polymer layer may have a double-layered or a multi-layered structure wherein a second and/or third conductive polymer layer is made of a doped polymer of a thiophene derivative. A method for making the capacitors are also described.

Abstract: In a disk reproduction apparatus, data recorded on a disk is read and converted into an electrical signal by a pickup, thereby generating a tracking error signal. The tracking error signal is converted into a digital signal by an A/D converter. The digital signal is converted into an analog signal by a D/A converter via a tracking digital equalizer. This analog signal drives a driver. An output from the driver drives the actuator of the pickup. The tracking digital equalizer selects the first mode of preferentially increasing the resolution of output data from the tracking servo circuit or the second mode of preferentially preventing an overflow of the output data. The equalizer processes the digital data from the A/D converter. An analog gain switching circuit is connected between the tracking digital equalizer and the driver to switch between the different gains set in accordance with the mode selected by the tracking digital equalizer.

Abstract: A data slice circuit which generates a EFM signal from a RF signal includes a clock signal generator circuit for generating a clock signal not synchronized with the EFM signal. The data slice circuit divides a clock signal not synchronized with the EFM signal, by a divider, to generate a clock signal for counting. The clock signal for counting is inputted as a clock into an up/down counter. Up/down count control of the up/down counter is performed on the basis of an output from a comparator. The comparator compares the RF signal with a reference voltage and outputs data "1" or "0" in accordance with the comparison result. A count output of the up/down counter is converted into an analog voltage by a digital/analog converter and is supplied as a reference voltage to the comparator.

Abstract: A library apparatus in which a plurality of cell drums are divided into two groups respectively placed on the left and right side of a recording/reproducing unit placed in a central part thereof. In this library apparatus, rails are placed in a direction along which the cell drums and the recording/reproducing unit are arranged. The conveying of media, which are contained in the cell drums placed on the left side of the recording/reproducing unit, is assigned to an accessor placed on the left side thereof. Simultaneously, the conveying of media, which are contained in the cell drums placed on the right side of the recording/reproducing unit, is assigned to an accessor placed on the right side thereof. A robot hand of each of the accessors is opened and closed by a turn of a motor. At that time, a power supply is turned off. Moreover, the robot hand is prevented by a locking mechanism from popping out of the accessor. Furthermore, ordinary cartridges are discriminated from cleaning cartridges.

Abstract: When a second switching element Q.sub.2 is changed over from ON state to OFF state for each switching cycle while a first switching element Q.sub.1 remains ON in a unit weld period T.sub.a for example, a primary current I.sub.1 does not come to a stop at once under the influence of inductance of a welding transformer 16 but it flows as a transient current i through a primary circuit until it is off. The transient current i makes a closed circuit through which it flows from a primary coil of the welding transformer 16 via a third diode D.sub.3 and then a first switching element Q.sub.1 again into the primary coil of the welding transformer 16. More specifically, due to the first switching element Q.sub.1 being kept ON, the transient current i which has passed through the third diode D.sub.3 flows through the first switching element Q.sub.1, without passing through a capacitor 12, and comes back into the primary coil of the welding transformer. Little or substantially no current flows through the capacitor 12.

Abstract: In a disc reproducing apparatus using a VCO (voltage controlled oscillator) circuit, the VCO circuit includes a first delay cell array having gates supplied with a first control voltage DCV, a ring oscillator including a second delay cell array having gates supplied with a second control voltage Vin, and a switch for selecting the number of delay cells from the second delay cell array. The oscillation frequency of the ring oscillator is determined by a time delay of the second delay cell array. When the second control voltage Vin having the same value as the first control voltage DCV is inputted to the gates of the delay cells of the second delay cell array, the ring oscillator oscillates with a frequency determined by the ratio of the number of the delay cells of the first delay cell array to number of the delay cells of the second delay cell array.

Abstract: A library unit including a plurality of frames and a plurality of cell shelves, each of the cell shelves having a plurality of cells arranged in an X-Y plane. The plurality of cell shelves are located in at least one of the plurality of frames, at least one accessor having a picker portion, and a plurality of first reference flags, each of which having substantially the same X-axis coordinate are provided with each of the frames with a spacing in the Y-axis direction. According to the library unit, the plurality of first reference flags are detected by a sensor attached to the picker portion, and a relative inclination angle of the accessor with respect to the Y axis in the X-Y plane is calculated from a difference in position in the X-axis direction of plurality of reference flags in order to obtain a correction value in the X-axis direction for each cell.

Abstract: A medicament for preventive and/or therapeutic treatment of hyperphosphatemia which comprises a pharmaceutically acceptable anion exchange resin such as a 2-methylimidazole/epichlorohydrin copolymer, cholestyramine resin, or colestipol. The medicament is orally available and has lowering effect on blood phosphate concentration and reducing effect on urinary phosphate excretion, and is useful for the treatment of conditions caused by hyperphosphatemia including renal dysfunction and the like.

Abstract: In order to improve the quality of seam welding, an inverter seam resistance welding electric power supply apparatus reliably determines local weldability (conforming/defective) of seam welding by simply monitoring welding current. In a seam welding operation, when a current monitor time interval has elapsed, a CPU reads, from storage, measured current values ?I.sub.1 !, ?I.sub.2 !, etc., of each inverter cycle obtained during the current monitor time interval and computes an average current value ?I.sub.M1 ! thereof, according to an averaging method such as an arithmetic mean method. Then the CPU compares the average current value ?I.sub.M1 ! with a preselected monitoring value or range. If the average current value ?I.sub.M1 ! falls within the monitoring range, the CPU determines the occurrence of a conforming local welding whereas it determines the occurrence of a defective local welding if the average current value goes out of the monitoring range.

Abstract: A solid electrolytic capacitor is composed of a pair of electrodes and a dielectric film therebetween, wherein one electrode includes a conducting polymer doped with a polyvalent anion and a monovalent anion. The conducting polymer layer may have a multi-layer structure wherein a second or third conductive polymer layer is made of doped thiophene or derivative thereof.

Abstract: Inverter-resistance welding control, for any resistance welding machine and for any welding operation, which guarantees a welding current having a quick rise time and which is free from overshoot. In particular, when a maximum allowable current value of the resistance welding machine involved has been entered and a selected current value of a particular welding operation has been entered, a CPU computes an initial pulse width of a control pulse from the maximum allowable current value and the selected current value. In a first cycle of the welding operation, the CPU supplies a first control pulse having the initial pulse width to the inverter circuit to thereby start the welding operation. The initial control pulse width is determined as a function of a machine current capacity and the desired current level of a welding operation, and may be made in proportion to a relative magnitude (ratio) of the desired current to the machine current capacity.

Abstract: An apparatus for an optical disk reproducing apparatus is disclosed, which allows positive counter-measures against data read errors without depending on only an operation of decreasing the reproduction speed, thus positively maintaining high speed reproduction. This system incorporates an error rate counter for monitoring error flags which can be detected in error correction processing, and a variable gain amplifier for adjusting the amplitude of an RF signal. A system controller constantly monitors error count data to determine the error rate of a disk in the reproduction mode from moment to moment. When the error rate exceeds a certain level at each reproduction speed, the amplitude of an RF signal from the variable gain amplifier is increased to set the error rate to a level at which data can be properly read.

Abstract: A library apparatus where multiple moving commands generated by several upper-order units are conveyed to a director. The moving commands may be sequentially conveyed through the same channel or may be simultaneously conveyed through different channels. The moving commands are then conveyed to an accessor controller which includes a real table and a plurality of virtual tables. The contents of one of the virtual tables is switched to the real table. Accessors are operative in accordance with the contents of the real table. The switching of contents from virtual tables to the real table enables the accessor controller to act as if two operation commands exist instead of one command so that a plurality of accessors can operate simultaneously.

Abstract: A tracking error signal is converted into digital data by an A/D converter. A compensation circuit performs gain and phase compensation operations in accordance with the frequency of the digital data. A kick signal generation circuit turns off a switch in access processing and outputs a kick signal. A comparator detects the magnitude relationship between output data from a filter and a reference level. During data read processing, a system controller sets the reference level at R1, detects the disturbance of the rotation frequency of a disk, and appropriately sets the compensation characteristic of the compensation circuit. During access processing, the system controller sets the reference level at R2, detects the moving amount of a pickup, and if the moving amount is large, sets the value of the kick signal to be small.

Abstract: An inverter resistance welding control or power supply apparatus includes a clock generator which generates a clock signal defining a switching cycle of an inverter in a resistance welding machine, a device for preselecting a predetermined reference value corresponding to a desired current peak, a current sensor for detecting primary or secondary current of the welding machine, and an inverter control for controlling the inverter on a switching cycle-by-cycle basis. Specifically, the apparatus turns on the inverter in response to a leading edge of the clock signal, and turns the inverter off either when the current detected signal has reached the reference value or when the clock signal has reached a trailing edge. The control apparatus further includes a magnitude evaluator for measuring a magnitude of the current from the detected signal, which magnitude is expressed in root mean square, arithmetic mean or averaged peak value.

Abstract: A library apparatus where multiple moving commands generated by several upper-order units are conveyed to a director. The moving commands may be sequentially conveyed through the same channel or may be simultaneously conveyed through different channels. The moving commands are then conveyed to an accessor controller which includes a queuing table for storing the commands. The queuing table permits the accessor controller to receive additional commands prior to the execution of the previous command. Therefore, the processing speed of the system is increased. Next, the commands are conveyed to a plurality of accessors which transfer the medium cartridges to the desired location. Several accessors may be operated simultaneously in parallel. The simultaneous operation of several accessors also increases the efficiency and speed of the system.

Abstract: A focus balance automatic adjusting device includes an adder, an envelop detector circuit, a disturbance generator and signal processing section. The adder adds together signals obtained by converting signal currents detected by a four-divided detector into voltages by use of first and second current-voltage converters to create an RF signal. The an envelop detector circuit effects the peak detection and bottom detection for the RF signal and creates an RFRP signal which is a difference between the peak detection signal and the bottom detection signal. The disturbance generator generates disturbance signals for deviating the focus position in positive and negative directions. The signal processing section receives the RFRP signal and the disturbance signal to control the gain of the second current-voltage converter.

Abstract: A pickup reads data recorded on a disk and outputs a current signal corresponding to the read data. An amplifier outputs the current signal as a voltage signal. A data slice circuit binarizes the voltage signal and converts it into an EFM signal. In response to the EFM signal, a PLL circuit generates a PLL clock signal in synchronization with a reproduction speed. When a reference speed or its two-times higher speed is selected as the reproduction speed, if the PLL clock signal is synchronized with the EFM signal, the frequency of the PLL clock signal is proportionate to the reproduction speed. In response to the PLL clock signal, the data slice circuit controls the frequency band of a reference voltage in accordance with the reproduction speed, and outputs the EFM signal. A data processing circuit demodulates the EFM signal and removes a jitter from the demodulated signal in response to the PLL clock signal.

Abstract: A pickup reads data recorded on a disk and outputs a current signal corresponding to the read data. An amplifier outputs the current signal as a voltage signal. A data slice circuit binarizes the voltage signal and converts it into an EFM signal. In response to the EFM signal, a PLL circuit generates a PLL clock signal in synchronization with a reproduction speed. When a reference speed or its two-times higher speed is selected as the reproduction speed, if the PLL clock signal is synchronized with the EFM signal, the frequency of the PLL clock signal is proportionate to the reproduction speed. In response to the PLL clock signal, the data slice circuit controls the frequency band of a reference voltage in accordance with the reproduction speed, and outputs the EFM signal. A data processing circuit demodulates the EFM signal and removes a jitter from the demodulated signal in response to the PLL clock signal.