Abstract: There is disclosed an electron beam metrological system which is inexpensive to fabricate but capable of accurately measuring the length of a circuit pattern formed on a wafer. The system comprises an X scan coil, a Y scan coil, an X scanning signal generator, a Y scanning generator, a detector for detecting secondary electrons emanating from a specimen when a rectangular region on the specimen is scanned by an electron beam in X and Y directions, a memory for storing the output signal from the detector, and a display unit for displaying an image of the rectangular region according to the data stored in the memory. The scanning generators are controlled by a CPU such that the scan made in the X direction is repeated plural times while the starting position of each scan is shifted in the X direction. The amount of the shift is so set that the beam hits the rectangular region at equally spaced positions. The signals stored in the memory in response to the repeated scan are used to determine the length.

Abstract: A method for manufacturing a packaged, aseptic hard soybean curd having high protein content and fine texture increased in hardness with keeping good taste which includes the first step of warming a soybean juice, adding 1-4% by weight of a soy protein isolate having a high coagulation ability, subjecting the soybean juice to a homogenizing treatment and sterilizing the soybean juice by direct steam heating method and the second step of continuously adding to thus obtained sterilized high protein soybean juice a germ-free coagulant solution at a constant rate in a pipe line and homogeneously mixing them, filling the mixture in a container in an aseptic atmosphere, sealing the container and heating it to coagulate the mixture. Thus obtained soybean curd has a hardness of at least 130 measured by a curd tension meter.

Abstract: An electrolytic capacitor which can be protected from rupture thereof due to an increased pressure of electrolytically generated hydrogen gas therein and can be continuously used over a long period of time, comprises an electrolytic liquid contained in a closed container, at least one pair of an anode foil and a cathode foil immersed in the electrolytic liquid, alternately superimposed on each other, coiled together and spaced apart by at least one insulating spacer to form an electrolytic capacitor, anode and cathode terminals being respectively connected to the anode and cathode foils and extending to the outside of the container, and a semipermeable membrane element arranged in a portion of the container and having at least one semipermeable membrane which exhibits, a hydrogen gas-permeating rate of 3.6 cm.sup.3 /cm.sup.2 .multidot.1000 hours or more determined at 50.degree. C. under a hydrogen gas partial pressure of 2 kg/cm.sup.2 and a water vapor-permeating rate of 2000 cm.sup.3 /cm.sup.2 .multidot.

Abstract: An electrolytic capacitor having very thin spacer layers is produced by a process in which at least two of the surfaces of an anode valve action metal foil and a cathode metal foil are coated with a photosensitive polymer resin solution; the resultant photosensitive polymer resin solution layers are solidified; the solidified photosensitive polymer resin coatings are masked with a negative or positive masking film having a desired pattern and irradiated with an actinic radiation to partly harden the photosensitive polymer resin coatings in accordance with the masking pattern; after removing the masking film, the irradiated photosensitive polymer resin coatings are developed with a developing liquid to provide spacer layers consisting of hardened portions of the photosensitive polymer resin coatings; the anode and cathode metal foils having the spacer layers are superposed on each other in such a manner that at least one spacer layer is located between the superposed anode and cathode metal foils and at least

Abstract: A melt-spinning nozzle in which is disposed an elongated molded piece so as to form a space serving as a melt flow path between the elongated molded piece and the inner wall of the nozzle.

Abstract: A formwork apparatus for concrete placing comprises: a center frame assembly having upper and lower ends; first and second form panels for molding concrete walls, each having a supporting member mounted on an outer surface thereof, the first form panel pivotally connected at its supporting member to the upper end of the frame assembly so as to be pivoted about a substantially horizontal axis, the second form panel pivotally connected at its supporting member to the lower end of the frame assembly so as to be pivoted about an axis parallel to a pivot connecting the first panel with the frame assembly; a first fixing mechanism for fixing and releasing the first panel to and from a cured concrete wall; a second fixing mechanism for fixing and releasing the second panel to and from the concrete wall; a first drive mechanism for pivoting the frame assembly around the first panel when the first panel is fixed to the concrete wall so that the second panel is brought to a position upper side of the first panel; and a

Abstract: A protective device for protecting a semiconductor integrated circuit from the destruction phenomenon which occurs due to an extremely high input voltage. The protective device comprises a protective input MIS transistor having a semiconductor substrate, a diffusion region formed in the semiconductor substrate, and an input electrode wiring layer electrically connected to the diffusion region. The input electrode wiring layer does not directly contact the diffusion region, rather, it contacts the diffusion region through a first polysilicon layer and a second polysilicon layer. The first polysilicon layer is formed on an insulating film adjacent to the diffusion region, and the second polysilicon layer is formed so as to be in contact with the first polysilicon layer and the diffusion region. The concentration of impurities in the first polysilicon layer is higher than that in the second polysilicon layer.

Abstract: A level converter circuit for converting a first logic signal using a lower voltage supply as a base potential into a second logic signal using a higher voltage supply as a base potential. The level converter circuit comprises first and second bipolar transistors, the base potential of the second logic signal being applied to the collectors of the first and second bipolar transistors, the emitter of the first bipolar transistor being connected to the base of the second bipolar transistor, and the emitter of the second bipolar transistor being used for the output terminal of the level converter circuit, and means for turning on the second bipolar transistor or both bipolar transistors in response to the first logic signal applied to the input terminal.

Abstract: A capacitor element is enclosed within a laminated film including at least a plastic film. The laminated film portion surrounding the capacitor element is heat sealed to form an enclosure structure sealing the capacitor element. The sealing width of the sealed portion formed by heat sealing is selected to be within the range of 1 to 20 mm. The thickness of the inner film of the laminated film opposing the capacitor element is selected to be within the range of 70 to 200 .mu.m. A capacitor of improved life time is obtained.

Abstract: A static semiconductor memory having a plurality of memory cells respectively connected to word lines and connected in parallel to bit line pairs and having a power-down function, is provided with a coupling noise canceller connected to a data bus which is connected at one end to a bit line via a transfer gate and at the other end to a sense amplifier. When the static semiconductor memory is placed in a power-down mode, the coupling noise canceller operates to clamp the data bus at a predetermined potential; thus preventing an increase in the access time when the chip is accessed from the power-down state rather than the active state.

Abstract: A semiconductor memory circuit having reduced read-access time and comprising a plurality of first and second common line pairs, each including a bit line and a data line connected in series is disclosed. Conventional static RAM memory cells are connected between each of the bit line pairs. A write-control circuit and sense amplifier are connected between each of the data bus pairs. At least one bypassing transistor is connected between each of the first and second common line pairs for conducting current between each of the lines of the common line pairs, thus reducing the read-access time.

Abstract: A semiconductor memory circuit is provided with a right memory cell group and a left memory cell group, word decoders corresponding to respective rows and; which are located between the right and left memory cell groups and which specify an address in the word direction of these memory cell groups, and column decoders corresponding to respective column which specify an address in the bit direction of these memory cell groups. The memory circuit also includes right and left memory cell group selection and drive gates for every word decoder and circuits for detecting whether the accessed memory cell is in the right or left memory cell group. The right or left memory cell group selection and drive gates operate in a complimentary manner and in accordance with the accessed memory cell being in the right or left memory cell group.

Abstract: An address buffer circuit which generates a pair of complementary signals for selecting a memory cell according to an address input signal is disclosed. This address buffer circuit comprises a short circuit device connected between a pair of output terminals for the complementary signals. During the stand-by period of a memory, the short circuit device electrically connects the pair of output terminals, so that the potential of both of the pair of output terminals becomes an intermediate level between high and low levels provided at the output terminals during the active period of the memory.

Abstract: A semiconductor memory device of an MOS static type comprising a current switching mechanism, such as depletion type transistors, arranged between a power supply and bit lines. The current switching mechanism is controlled by column selection signals and supplied a larger current to the bit lines during the selected mode than the non-selected mode.

Abstract: A method of manufacturing a packaged soybean curd with a long shelf life without the inclusion of any artificial additives such as coagulating agents, germicides and the like; wherein soybean juice is subjected to lactic acid fermentation until its pH is reached to a value equal to or less than a value which is determined from the percentage of the solids content (5-16 wt. %) of soybean juice and then is subjected to heating (60.degree.-95.degree. C., 10-100 minutes) to adjust the curd tension to above 20 g.

Abstract: Disclosed is column decode circuit for a random access memory, which column decode circuit is comprised of a conventional transfer gate transistor, conventional driver transistors and a conventional load transistor. The column decode circuit further includes a chip enable gate transistor according to the present invention. The conventional gate transistor transfers data stored in a corresponding memory cell of the random access memory in accordance with a column address information. The column address information received by the conventional driver transistors connected in parallel causes the above gate transistor to be conductive or nonconductive. Accordingly, the conventional load transistor will apply a voltage of a particular voltage level (Vcc) from a voltage supply to the gate of the transfer gate transistor. The chip enable gate transistor, the load transistor and the parallely connected driver transistors are all connected in series.